Design And Verification Of DDR3 Controller On Communication SoC

In a computer system,the memory is a very important component.Because of the existence of the memory,the computer has a "memory" function to be able to work normally.In many types of memory,the memory has a decisive effect on the performance of the system because the system runs externally stored data in memory during operation.In recent years,the rise of big data and artificial intelligence,in order to be able to handle massive amounts of data quickly and efficiently,has required increasing memory capacity and frequency.The memory controller determines the type of memory that the chip can support,and converts the fetch request into a command format that meets the memory protocol requirements.Therefore,it is very important to study the memory controller to improve the system performance.The dissertation studies the structure of the communication SoC chip and deeply analyzes the technology applied in the chip design process,including SoC technology and AMBA bus protocol specification.At the same time,the structure and working principle of DDR3 SDRAM are studied.In order to meet the needs of the chip storage data,through the analysis of the chip structure and DDR3 protocol,a DDR3 SDRAM memory controller design scheme supporting AXI bus interface is proposed.The designed controller can be flexibly configured for different application scenarios.The controller is first divided into a protocol control layer and a physical layer.The protocol control layer is composed of an access interface module,a configuration interface module,an initialization module,an instruction reordering module,a non-read-write instruction generation module,an instruction control module,a data processing module,and a DFI interface module.The functions of these modules are analyzed and then used.Hardware description language design internal logic.In order to reduce the design difficulty of the controller and reduce the design cycle,the physical layer of the memory controller is directly connected with the protocol control layer in an IP-based manner.Then,a virtual prototype verification and FPGA prototype verification are performed on the memory controller on the built SoC verification platform.Finally,the simulation results are analyzed to ensure that the designed controller functions correctly.The designed controller improves read and write efficiency to some extent.By analyzing the working principle of the memory,when accessing the memory,the controller caches the fetch request from the bus,and then compares it with the previously cached commands in the Bank state table and the sorting queue,and reorders the current enqueuing commands according to the comparison result.This improves read and write efficiency.Taking into account the high frequency of read and write operations may have errors in the data,the design of additional check digits to achieve error detection and correction functions.In FPGA prototype verification,because the physical layer in the controller cannot be synthesized,the Xilinx PHY is used to replace the PHY in the controller for verification.However,the Xilinx PHY does not support the DFI interface.Therefore,the DFI2 PHY protocol conversion module is designed.Later,we provide a reference for FPGA prototype verification of the memory controller.After verification,the controller can successfully access two types of memory chips,DDR3-800 and DDR3-1066,to meet the data storage management requirements of the communications chip.