The Design And Implementation Of FPGA Prototype Verification Platform's Memory System

During the past half a century,the integrated circuit industry pushed by the demands from daily life or other industries has made significant progress.As the number of transistors on a single chip increases rapidly,the design complexity of common integrated circuits also climbs to a very high level.In this case,functional verification of one chip,one key step of the design flow,becomes more and more difficult.It is very important and challenging for the chip design to achieve efficient verification.In this thesis,we do some research on the FPGA prototype verification platform.The design and implementation of the memory system is our emphasis.The thesis presents the internal memory system's DDR3 controller and the external memory system's SD controller of the whole platform.According to our project,we give the test plan of the internal and external memory system.The main contributions and work can be summarized as follows:1.The design and implementation of the internal memory system's DDR3 controller for the FPGA prototype verification platform.As a high-capacity and high-speed memory device,the DDR3 memory plays an important role in the FPGA prototype verification platform.Operating system and large-scale test programs both rely on it.In this thesis,we discuss the structure,the features and the operating principals of DDR3 memory.The thesis presents a DDR3 controller with AXI4 bus interface.Finally,functional verification and test illustrate the correctness and effectiveness of this DDR3 controller.2.The design and implementation of the external memory system's SD controller for the FPGA prototype verification platform.SD card is widely used because of its great-flexibility,high-security,high-capacity and high-speed.The FPGA prototype verification platform needs urgently high-capacity and high-speed external storage for storing operating system and large-scale test programs.After discussing the SD card communication protocol and APB bus protocol in-depth,this thesis designs and implements a SD card controller based on FPGA prototype verification platform.Finally,hardware-based test illustrate the correctness and effectiveness of this SD card controller.3.Test of the FPGA prototype verification platform's memory system.The FPGA prototype verification platform's memory system provides support for large-scale,high-speed tests.To test of the verification platform's memory system,this thesis presents a detailed test plan of the memory system.We discuss and analyze the benchmarks for our test.Finally,the test results prove the correctness and effectiveness of the FPGA prototype verification platform's memory system.In summary,the thesis investigates the DDR3 controller,the SD card controller and the test of the FPGA prototype verification platform's memory system.It has significant practical values in promoting the advancement of research on the FPGA prototype verification platform.