Design Of Memory Controller IP Core And Its Validation On FPGA

As a part of the computer system, memory performance directly affects the computer system performance. Because memory cannot recognize the command sent from CPU, memory controller is in charge of processing these commands. It determines some key parameters which are the computer system supporting such as maximum capacity, the number of banks, memory type and speed, the depth and width of SDRAM and so on. Therefore, memory controller determines memory performance or even the overall system performance. Focusing on memory controller research becomes one of the hot points in some fields such as High Performance Computing (HPC), embedded system and so on.Based on researching on the DDR3SDRAM JEDEC standard JESD79-3E, the thesis introduces the key technology and the read/write principle of DDR3SDRAM at first. Then taking the external memory interface solution of Altera Corporation for reference and taking the features of embedded system into consideration, argument on the controller design plan, after that, the top architecture of the memory controller is designed. Continuing, with the top-down and modular design methodology, the DDR3memory controller is spitted into10sub-modules and realized by programming with VHDL language.After finishing the design of memory controller IP core, a test bench is designed for validation at first. Software simulation is executed in the Quartus Ⅱ10.0SP1and Modelsim-Altera6.6c start edition. In addition, the thesis gives the RTL simulation results and result analysis of some key modules such as user interface module, initiation module and execute module and so on. After software simulation, a debugging experiment is executed on the development kit which is equipped with Altera Stratix Ⅳ family FPGA.The memory controller IP core which is designed in the thesis has the following features:(1) It supports the overall series of Unbuffered ECC or Non-EC C memory modules (UDIMM), which capacity can up to8Gigabytes.(2) It can recognize the module automatically and free to setting parameters, which can save much time and jobs for users.(3) It supports the peak speed of800MHz and the peak bandwidth of8500Mbps.(4) It supports Altera ALTMEMPHY interface.(5) The IP core can apply to embedded system. It is smart and easy to transplant.