Design And Implementation Of DDR3 Memory Controller

With the increasing demand of high performance in signal acquisition and processing and computing in data, which make Double Data Rate(DDR) memory system can’t satisfy the demand of data transmission. To research the way which can improve the DDR performance and transmission efficiency have an important theoretic and practicality value.XDSP processor is a high-performance Digital Signal Processor(DSP), which independently designed by National University of Defense Technology(NUDT), it will be widely used in high performance computing, wireless communication, video and image processing, etc. We designed and implemented DDR3 Memory Controller Based on the project of XDSP processor. The main research work and innovations are as follows:Firstly, we introduced the development and future trend of DDR memory, described the internal structure and addressing principles of DDR3 memory, analyzed the characteristics and performance of DDR3 memory and purposed the design needs of memory controller in order to enhance the efficiency of DDR3 memory.Secondly, based on the project background of XDSP processor, We designed and implemented Memory Controller, introduced the design of asynchronous transmit, configuration channel, storage channel and protocol conversion. We described implementation of the design in detail.Thirdly, we designed and implemented of DDR3 Memory Access Scheduler purposed the location allocation strategy, rotary arbitration, fixed priority, simulation stack arbitration and fetches data separation. Location allocation strategy balanced allocation request and improved the scope of the arbitration; Simulation stack arbitration implemented the design of arbitration and ensured the correlation between requests; Separation mechanism enhanced the rate of request transmit. Verification results show that Memory Access Scheduler improves the access efficiency of DDR3 memory.Finally, we verified and implemented the Memory Controller, verified results shown that the functions of Memory Controller are right, it reached the coverage efficiency convergence. We synthesized the Memory Controller with Cadence RTL Complier tool in 40 nm CMOS technology by RC at the condition of Typical. The synthesis results shown that the timing delay, area and power achieved the design goal. We analyzed the bandwidth utilization of Memory Controller. The results shown that the bandwidth utilization achieved the design requirements, Memory Controller improved the access efficiency.