The Improved Design Of Functional And Verification Of NOR FLASH Chip's Write And Erase Controller Based On CFI

With large storage capacity,fast read and write,good nonvolatile data,low cost,good parallelism and other features,Flash has become one of the most popular products in domestic and international IC market.Now,most of the mainstream products of NOR Flash chip companies in C hina are based on Serial Peripheral Interface other than the Common Flash Interface,because the later started relatively late and domestic chip manufacturers almost have no mass production of such products.Therefore,how to design and develop lower cost and higher performance of NOR Flash chips which is based on the Common Flash Interface is very important to the promotion of FPGA,SOC and other areas of the chip and development of related industries.This paper designs and implements an erase and write controller of NOR Flash memory chip.Compared with the characteristics of traditional erase and write controller of NOR Flash memory chip,we added new block lock down operation to reduce the possibility of internal data error caused by the misuse based on the traditional erase block lock operation and remove block lock the operation,which is in order to achieve erase protection to a single block module within the chip,and avoid misuse.Based on the traditional program operation,this paper designs and improves the Multi-Program operation,Fast-Program two write modes,which can meet the user's various write requirements,reduce the writing time and improve the efficiency of the chip.Finally,on the basis of the basic erase operation,it is possible to realize a multiple operation combination of some fixed operations,such as program suspend,resume,erase,write and read operations.These designs increase the practicality of the chip in a large extent.First,for the problem of poor transplantation in traditional VMM verification platform,we establish a verification platform,which has high reusability,and it can also be compatible with ST authentication and UT authentication to realize Double-checker.This platform can meet the needs of verification of the most current flash chips.Second,in order to oversee the DC signal combination of Flash chips,and resolve the problem of time consuming in traditional SVA verification,we add double SVA monitoring switch.It makes SVA components can be very convenient to achieve the overall called and disabled,and some of the Assertions in the SVA component can be turned on or off from the test case,which greatly saves the time of simulation of the test case and accelerates the verification progress.Finally,according to the different test cases corresponding to the verification objectives and we add an independent coverage group in the test case to ensure the completeness of functional verification.The final coverage of the flash chip designed in this paper is 92.59%,and tape out.From the test results of the completed chip,we know that it has a greater improvement in the erase operation performance compared with the current common flash chip.The time cost of 32 K Word erase is reduced from 1.2s to 0.59 s,and the time cost of 32 words write is reduced from 384?s reduced to 241?s.