Verification Of Memory Chip's Read Controller Based On Parallel Flash Standard Interface

In recent years integrated circuits have a rapidly development,Flash performance have been improved constantly,In order to adapt to the rapid evolution of integrated circuit manufacturing technology,improve the market competitiveness,the requirement of flexibility about data operation of Flash is more and more strict.Problems of data storage and management are gradually revealed,to establish a rapid,accurate,diversified reading mechanism of memory data is imminent.At the same time,with the increasing number of complex modules that can be integrated on the same chip,the scale of the digital logic is bigger and bigger,which drastically increased the difficulty of the chip's verification work.How to build the Flash test platform reasonably,Complete validation work efficiently,have very important significance on the research and application of Flash.This thesis is emphasized on the read controller verification which based on the parallel standard interface of Flash memory chip.In-depth study the design function of read controller,synchronous and asynchronous two read ways of read controller,and circuit design of storage arrays,status and the configuration registers etc.structure to read the data are introduced in detail.Synchronous read is divided into continuous read and the single read.through deploying the configuration register can configure read mode,handshake signal polarity,data maintain cycle,the length of reading,the information of the wrap.The chip also have the function of reading storage array,reading status register and the configuration register,etc.data structure.In this way,data read operation will greatly enhance the flexibility and diversification.Based on the above design,set up the verification platform using the verification language named System Verilog and the verification methodology VMM,and set up the verification platform with hierarchical structures,each layer collaborated to complete verification of the design under test.According to the requirements of the design of the Flash,extracted the points.According to the extraction of the verification point wrote the corresponding constrained random test vector,used the VCS to simulate,then analyzed the abnormal waveform,found design flaws.Joined the test vector which ran successful to the recursive test library,carried out a large number of the recursive test on the Flash,found the boundary errors of design as much as possible.Finally collected function coverage and code coverage,through the analysis of functional coverage,determined whether completely covered all of the function point of validation.Based on the verification platform,this thesis developed more than 200 test vector in total,in the whole process of regression test 1 million seeds were randomly generated and 27 design flaws were found.The final collection of function coverage reached 100% and the code coverage reached 97.32%,which met the design requirements.The verification platform which is set with the advanced verification language(System Verilog language)and the VMM verification methodology has the reusable automatic function and the commendable inheritance,Use the top System Verilog language and VMM authentication methodology of building verification platform with high reusability,good inheritance,and support the incentive constraint random,the result can be automatically compared.This scheme can greatly reduce the workload of validation engineer,improve the efficiency of verification efficiency.And these have very important significance on the availability and smoothness of later projects.