The Verification Of Flash Controller Module Based On UVM

As the cornerstone of modern electronic information industry,Integrated Circuit(IC)plays an important role in modern society.And with the increasing sophistication and complexity of So C design,the verification takes most of the total time which So C design work spends.However,because of the backward chip verification technology,it is imminent to find an advanced and efficient verification method.The core of chip verification is verification methodology.As the latest verification standard in chip verification industry,UVM(Universal Verification Methodology)is a suite of high-performance verification environments developed based on the System Verilog language which combines the features of Verification Methodology Manual(VMM)and Open Verification Methodology(OVM).NAND Flash,due to its advantages such as low cost,high density and physically non-volatile mechanism,has been widely used in the storage industry.Therefore,according to the characteristics of Flash controller in So C chip,this thesis uses used the UVM to establish the verification platform of Flash controller module.At first,this thesis analyzes the development of UVM.Then,we introduced the verification theory and UVM verification methodology,which focuses on the package components and the characteristics of verification platform.After that,this thesis uses UVM to develop a verification program and determines the structure of UVM verification platform according the test points.Finally,this thesis specifically implements every component of UVM verification platform using System Verilog language,and set up UVM verification platform of the Flash controller module successfully.Besides,this thesis invokes all kinds of test case with stochastic constraints to the Flash controller module,ensured the validity of design of controller module Flash.In summary,code coverage rate of this validation simulation reaches 95% and the function coverage rate reaches 96%.It shows that the verification platform is sophisticated,and we achieved the purpose of verification,and it also can be reused in a variety of solid-state equipment master chip verification platform because of the high portability.It proved that the UVM verification methodology had advantages in today's integrated circuit design flow because of its flexibility and reusability.