The Research And Implementation Of Multi-Core DSP Debugging System Based On JTAG

More core can be integrated on a chip along with the development of IC technology, and the single chip system comes out which is called system on chip(SOC).The appearance of SOC makes a chip have more complex function and get higher performance, but also makes the observation and controllability to the internal signals of a chip difficult. Adding the DFD(Design For Debug) to improve the observability and controllability of SOC becomes more and more important.This paper focuses on the multi-core DSP debugging system, completed the design of the debugging system. Firstly introduced the embedded debug features, compared the commonly used method of embedded debugging advantages and disadvantages; secondly describes the JTAG debugging principles, including the boundary scan chain and the TAP controller working principle and process, and then introduced a number of JTAG devices interconnected structure. In the multi-core DSP debug hardware, we design a multi-core DSP debug interface which can control the processor single step running, breakpoint debugging and running.GDB porting is another focus of this new processor architecture. GDB has good portability, not only can quickly obtain powerful debugging capabilities, but also reduce the development costs. This paper studies the structure of GDB, the technology involved,including representation and extract the executable file format, debugging information, GDB operational mechanism, and gives specific steps and GDB transplant program.GDB communicate with a remote chip need to protocol conversion. This paper also studied debug agent software which functions the protocol conversion. Debug agent software do not take up the target machine resources, has good flexibility and ease of use. In the analysis of the software needs and process, we design and impletement the debug agent.Finally, we give functional verification result of the debugging system based the simulator.