Multi-core Processor Debugging System Based On Instruction Insertion

Any processor and circuit system need boot code, operating system and application program. These programs need to be developed and transplant. With the improvement of processor integration and complexity, the corresponding program design and debugging has become increasingly difficult. Debugging of large programs cannot perform without a good processor hardware support, especially in the boot code and the operating system debugging. Researchers have proposed a variety of debugging techniques and method, some technology has been widely used in software development, such as ICE, debugging agent, software simulation, etc. But these debugging techniques are lack of support to the current mainstream of multi-core and multi-threaded processor. A multicore debugging system based on the instruction insertion method is provided in this paper. The design and implementation of multi-core processor debugging system is based on asynchronous interconnection structure, and its innovations and the main work are as following.1) Proposed reusing commit stage signals of the core pipeline to implement matching and processing of the data breakpoint, instructions address breakpoints, instruction breakpoint. Due to out-of-order features and multi-shot features of the pipeline, the instruction address breakpoints matching in fetch stage will inevitably lead to false trigger breakpoints. How to solve this problem is the key to debugging support parts design. This paper presents multiplex pipelined instruction commit stage signals to solve the instruction address breakpoint matching error problem, bypassing the complex pipelined execution behavior analysis. The design scheme is applicable to all kinds of sequential committed processors.2) Design and implementation of core debugging support unit(DSU) based on the instruction insertion method. DSU makes full use of the core pipeline components and reconstures some stages to implement instruction inserting at low hardware cost. DSU receives commands from the debugging host, performs execution pauses/run control, setting of instruction/data breakpoints, setting of hardware/software breakpoint, variable observation or updating.3) This paper presents an on-chip asynchronous interconnection protocol, i.e. CLB. The debugging system of the multi-core processor X3 is based on CLB. This multi-core debugging system transforms the debugging commands from off-chip ICE to DSU in every core. The host debugging software uses the open source Eclipse and GDB, which makes the system capable of cross debugging with graphical user interface.