The Design And Implementation Of JTAG Debug For Embedded Multi-core Processor

With the development of Multi-core processor technology, more and more research works are devoted to development and debugging tools. To raise the performance of processors, it is not enough to depend on the powerful chip but also need efficient method and debugging tools to ensure that both software and hardware developers can work in progress in an integrated Multi-core system environment. JTAG technology is still the leading debug tool for Multi-core processor. So how to debug cores integrated in Multi-core processor with JTAG and resue the orginal on-chip hardware and software of it is becoming an importment subject in Multi-core debug design.In this dissertation, we take QDSP as our research platform and study the JTAG debugging method in Multi-core processor technology. We mainly study the daisy-chain and TLM methods. As both of them can not reuse the on-chip hardware and debugging tools of the integrated cores, a new method that integrates a debugging support module in Multi-core processor is proposed. JTAG Server which designed in QDSP based on the method proposed in this paper needs debug tool to support it, so a JTAG emulator based on USB 2.0 interface is designed and implemented. On-chip Trace is an effective component of QDSP in on-chip debug work, based on which Trace Analyzer is implemented. All works did in this dissertation provide completely support for the debug system of QDSP including reliable on-chip debug module, high available JTAG emulator and Trace Analyzer.