The Implementation Of De-interlacing Algorithm On FPGA

With the promotion of high-definition television(HDTV), the customers have higher requirements for video quality. The resolution of traditional PAL video is too low that it makes people feel uncomfortable when displayed on digital video. Meanwhile, blur image and saw-tooth phenomenon caused by interlaced scanning make the image look worse and thus affect the aesthetic feeling actually displayed in engineering practice. The conventional DSP for de-interlacing in engineering practice is not only cumbersome but also resource wasting. Therefore FPGA is adopted to de-interlace video image.To start with, this paper introduces related knowledge about FPGA, and different kinds of de-interlacing algorithms are compared and illustrated detailed. Some improvements are made after comparing and analyzing different algorithms. An applicable algorithm and its FPGA implementation are presented in this paper.The algorithm in this paper is achieved by first using 4-field data to conduct the first motion detection, and at the same time implementing corresponding intra-field interpolation operation. Then use intra-field interpolation data to conduct the second motion detection, classifying all pixels into stationary points and moving points. Finally, the result of de-interlacing is obtained through a selection of different values. The algorithm is divided into specific modules after evaluating the resources of it. Related operations about DDR2 SDRAM chip and the operating method of the IP core of its controller are studied. Modules implemented by VHDL are downloaded to the board of FPGA for operation.The result is displayed in real time. By observing the de-interlaced images, we can conclude that the proposed algorithm can effectively eliminate phenomenon like blur and saw-tooth. Thus the reliability and superiority of the implementation of FPGA scheme is proved.