Design Of SDRAM Controller And Its Application On FPGA

High-speed data acquisition processing system is necessary in national great science engineering HIRFL-CSR(Heavy Ion Research Facility at Lanzhou-Cooler Store Ring) control system.The control system usually use cache memory as data buffer. SDRAM (Synchronous Dynamic Random Access Memory) is the best choice with the characteristic of high integration, low power, high reliablity, strong function. But SDRAM has complex time sequency. In order to reduce the cost, we design and realize SDRAM controller by using very popular EDA technology at present, choosing FPGA(Field Programmable Gate Array) used widely in the programmable logical device, using hardware description language VHDL (Very High Speed Integrated Circuit Hardware Description Language) and following advanced top-down design idea.The introduction outlines the CSR control system and points out the origin of the topic and its practical significance. The second chapter firstly introduces the survey and the performance target about memory, secondly describes the basic time sequency of DRAM in detail, finally discusses SDRAM exhaustively, including performance, characteristic, structure as well as some important operations and time sequency. The next two chapters separately discusses hardware design and software design about this topic and introduces the concrete chips and the FPGA design technology with emphasis. Chapter Five prestents its classical application, namely synchronous event processor of the SDRAM controller used in CSR control system. Finally summarizes this article.In the article we discuss mainly on the design principles and the ways of implementation. By the analysis of the testing results, the control system is approbated.