Design And Implementation Of Assembly Tool Chain For Application Specific Instruction-set Processor Based On LISA

In recent years, Wireless Sensor Network (WSN) has been widely used in military, home automation, medical, etc. Though, power is still one factor which has restricted the practical use of WSN. Meanwhile, Technology of general-purpose processor and its intellectual property are owned by a few foreign semiconductor companies. Thus, developing dedicated microprocessor for wireless sensor network with self-intellectual property has very important significance, for mastering the core technology of WSN and a better development of WSN filed in china. Furthermore, it helps to break the monopoly of foreign semiconductor company in this filed. TRIC is a transport-triggered architecture (TTA) based application specific instruction-set processor (ASIP), designed for Wireless Sensor Network (WSN) applications. In addition to a general-purpose instruction set, it has a dedicated instruction set that deals with MAC and HWCP routing. For a processor, it must have a series of supporting software tools to develop applications.This work has done an in-depth analysis the architecture of TRIC processor as well as processor modeling by the use of a processor architecture description language LISA. Then, taking TRIC as the targeted processor, this work designed and implemented its simulation model using LISA, which included resource model and instruction set model. The model was then used to generate the assembly tool chain for TRIC. Verification has been done to test the assembly tool chain. It turned out that every tool in the tool chain could properly fulfill its intended function. In the end, this work developed an integrated development environment for this assembly tool chain. For the assembly system build for TTA based ASIP in this work, when the application specific processor’s instruction-set changes, it will be very convenient to develop the new assembly tool chain. It could be easily achieved by a corresponding modification of the instruction-set model. This results in reduces of work and with high development efficiency. This work could play a guiding role of similar research work that needs to model application specific instruction-set processor and to develop its supporting software tools.