An Improved FMA Architecture With Reduced Error Of Iterative Arithmetic

In the design of a new generation of application-oriented multi-coremicroprocessor, designers introduce fused multiply-add (FMA) units in order tosignificantly improve floating point performance. There is only one rounding operationin the fused multiply-add unit and its advantage is to reduce the error of the result,which is different from the situation that floating point multiplier independentlyperforms with floating point adder. However, with the number of operationssignificantly increasing, iterative error will rapidly increase, which can seriously affectthe result. In this thesis, some research has been done on an improved FMA architecturewith reduced iterative error (IM-FMA) based on traditional fused multiply-addarchitectures (T-FMA).The following work has been finished in this thesis:1) Do some research on the current FMA algorithms and architectures, as well asthe impact of operation error in large-scale numerical calculation, analysis thedistribution characteristics of the system of floating point number–the uniqueness ofthe normalized number and the uniformity within the finite interval, calculate theMRREs and ARREs of different data formats based on logarithmic distribution andsummary the knowledge of binary data formats depicted by IEEE754-2008, exceptionhandling and error analysis.2) Establish the mathematical model applicable to the error analysis of iterativefloating point arithmetic, and derive the factors leading to iterative error–the number ofoperations (n) and round-off unit (u). Obviously, the fact is that the smaller round-off,the smaller iterative error. It is easy to make the conclusion that the fundamental methodto reduce the iterative error is to reduce round-off unit.3) Propose an improved FMA architecture with reduced iterative error (IM-FMA).Compared with T-FMAs’ result (53bits), the feedback path to the addend bringing withthe intermediate result (106bits) between normalized shifter and rounding operation isadded to the IM-FMA and then IM-FMA can choose the addend by distinguishingsingle arithmetic mode from iterative arithmetic mode. Besides, this thesis has donesome research on the algorithms, structures and logic circuits implementation of key unitsof the IM-FMA, such as multiplier unit, addend shifter and leading zero anticipationunit.4) Finish verification and test work of T-FMA and IM-FMA, and then execute twoiterative test sequences for T-FMA and IM-FMA. The absolute error and relative errorof T-FMA result of the first test sequence are252100and1.1102E-14, respectively.Meanwhile, both the absolute error and relative error of IM-FMA result of the first testsequence are0. The absolute error and relative error of T-FMA result of the second test sequence are252100and1.1102E-14, respectively. Meanwhile, the absolute errorand relative error of IM-FMA result of the second test sequence are100and2.4652E-30, respectively. Thus, the conclusion can be made that IM-FMA can reduceiterative error compared with T-FMA.