The Research And Implementation Of Double Data-path Fused Floating Point Multiply-Add Supporting Parrall Multiply

The fused floating-point multiply-add operation treats the multiplication and theaddition as an inseparable operation. There is no need to round the internal results, andthe precision of the result is improved. In addition to the above advantage, the delay ofthe operations and the cost of hardware implementation can be cut down. The fusedfloating-point multiply-add unit can realize most of the basic floating-point operations,and it has been becoming the key component of the high-performance processor.With the development of the multi-media technology, the multiplier has to supportthe parallel processing and the SIMD operation.This thesis proposes and realizes a new floating point multiply-add fused structurebased on the double data-path fused floating-point multiply-add, and it can supportparallel multiplier.The thesis does the research and development in the following fields:1. A new double data-path floating-point multiply-add fused structure ispresented and implemented. The fused floating-point multiply-add architecture logic isvery complex and has a long latency. In the design of this thesis, the floating point addinstruction and floating point multiply-add fused instruction do not flow the samepipeline stage, the floating point add instruction can be carried out three stages earlierthan the floating point multiply-add fused instruction.2. A parallel multiplier is designed. The 64-bit vector integer multiplier uses a"shared segmentation" method, and it can support multiple precisions. The vectormultiplier can perform one 64b×64b,two 32b×32b,four 16b×16b or eight 8b×8bsigned/unsigned integer multiplication using essentially the same hardware as a 64 bitscalar integer multiplier.3. An algorithm of Leading Zero Anticipation is improved. The most usedalgorithm in floating point adder and floating point multiply-add fuse component is"leading one prediction with concurrent correction method". The thesis point out awrong in that algorithm, propose a correction method and prove correctness of themethod.4. The test scheme of the design is proposed. The design has passed the test ofIEEE CC754 standard testing vectors, the special data for every instruction, theboundary and random testing vectors. It also has passed the test of the coherencebetween the behavior level and RTL level.5. The design methodology of the design's IP core is studied, including the modelof behavior level, the high coverage test vectors and the source code of the design.This thesis carried out the synthesis and optimization of the double precisionfloating point multiply-add fused component. The floating point multiply-add fused operations flow 9 pipeline stage and floating point add operations flow 6 pipeline stage.The synthesis result shows that the design can work at above 500MHZ, satisfying therequirements of X microprocessor.