The Design And Implement Of Floating-point Fused-multiply-add Unit For High-performance Microprocessor

Floating-Point Fused-Multiply-Add (FMA) unit as one of the kernel computingcomponents in high-performance microprocessors has great effects on the floating-pointperformance of the entire microprocessor. The algorithm of floating-point FMA iscomplex, so the latency of the FMA logic is especially long, and corresponding logicblock is very large. Complete verification of the FMA is very difficult and the designperiod is very long. Therefore, researches on the high-performance Floating-Point FMAare of important practical significance and broad application value.This paper has made some researches on the design and optimization techniques ofhigh-performance Floating-Point FMA unit, which is part of the major national project"High-Performance X Processor". The achievements will be directly applied to theproject. Based on the single-data-path algorithm of FMA, without trap and SoftwareAssistance, a FMA that supporting subnomals, signed zero, infinity and NaNs isdesigned, which aims at high clock frequency, small area and IEEE754Std.compatibility. The main research work and achievements are as follows:1. Comprehensive researches on the high-performance Floating-Point FMA unitand its key techniques are done. Based on this, a Floating-Point FMA unit of thehigh-performance X processor is designed and implemented.2. Proposed a carry correction structure for the multiply array, and designed amain adder based on the EAC architecture, which reduced the logic levels and improvedthe speed of FMA.3. Designed a simplified LZA architecture allowing subnormals fire or outputwith maximum normalization controlling and smart1-bit normalization correctiontechniques. Merging the exact infinity operation and NaNs data-path in the alignedaddend data-path, and combining the subnormal operands with the normal normalizeddata-path to share the mantissa data-path as much as possible.4. Completed the pipelined RTL model of the proposed FMA by Verilog HDL.The entire design is tested through a variety of inputs, including IEEE754standard testvectors, corner numbers and random vectors, which guarantee that the design has nodesign error.Finally, we synthesized and optimized the Floating-Point FMA. At40nm bulksillicon CMOS process, with worst process conditions, the results of logic synthesisshowed that the frequency of the Floating-Point FMA can reach2.5GHz and the area is56735.9um2, which meet the requirements of the X processor properly.