Research On Floating-point Multiply-add Fused Units And The Algorithm Based On FPGA

With the rapid development of the domestic CPU, high-performance floatingpoint multiply fusion research,which has independent intellectual property, is significant for improving performance.This paper has fulfilled the design of floating point multiply-add system to reduce the path delay through in-depth analysis of the throught and structure.The system has divided into the following main modules:decoding module, the multiplier module, adder module, leading-one prediction module, as well as normalization and rounding module, which the leading-one prediction is the key algorithm in the system to reduce the path delay.The most important innovation is the design of leading-one prediction module. A method is adopted to deal directly with three-operand on FPGA platform and designed three-operands complete prediction algorithm implemention. This method can reduce the critical path delay and power consumption. The paper focused on the design of three-operands encoding tree structure, and based on the pre-encoding rules on FPGA hardware verification platform, reasonable modular for system architecture, using hardware description language VerilogHDL to program some function module to optimize the design process and finally the results are analyzed and verified. Compared with the design using the traditional algorithm,the one using the proposed algorithm can reduce the delay of the critical path by36.15%,and reduce power consumption by 39.20%.Finally, the paper has completed the design of floating-point multiply-add integration system architecture in the basis of floating-point multiply-add components.The verification results showed that floating-point multiply-add fused structure effectively reduced the latency.