The Design And Implementation Of10Gbps Bit Error Ratio Tester

With the rapid development of optical communication system towards large-capacity, long-distance and high-speed, and the continuous improvement of optical communication access technology, the transfer rate change quickly, also optical module of10G rate, has been put into large-scale commercial application, have come into being. In this paper, a FPGA-based10G BERT is introduced as a kind of transceiver, which combines bit-error test function with error analog function. Meanwhile, according to the special requirements of the10G XFP optical module interface and the multiple-electrical interfaces, the author developed a low cost and practical error module.Compared with traditional one, this optical communication BERT has the following characteristics. Firstly, PRBS code line can be continuously adjusted from PRBS3to PRBS31to be applied in testing under different conditions. Secondly, the BERT stream rate is also adjustable, ranging from9.953Gbps to11.37Gbps. Thirdly, the BERT provides both XFP socket interface and SMA interface that can be used as XFP optical module BER tester and ordinary BER tester. Fourthly, it supports a variety of loop-back mode, by passing through, one can achieve long-distance test, and the input and output two-way can be negated. Fifthly, it allows manual insert, not only for single error, but also for equidistant insertion error. As a result, is has random distribution characteristic.Chapter Two has a brief introduction of the principle of BERT. As the discussion of the overall design scheme, Chapter Three elaborates the design of hardware. The content of Chapter Four to Six are the specific design as well as the simulation of bit error tested module, which include the bit error generation and contrast module, the network-interface module based on the SFI4.1protocal, and the control module. The result and data of measurement was supplied in Chapter Seven.This paper introduces a FPGA-based lOGbps Bit Error Tester plan in detail, With Altium Designer, the author completed schematic and PCB design, and completed the error test modules design in Xilinx Virtex5by Verilog HDL language. It includes the following aspects:1) EPP communication between FPGA and MCU.2) According to user settings, it brings in a PRBS sequence with a corresponding length and rate, and counts out the number of the errors and time.3) The analog channel function, and manual error insertion.4) Two types of loop-back modes in the error test module (three types outside).The BERT has been tested in the electrical eye diagram under the PRBS31pattern with different rate, and the results at1000test point show as follows:RMSJ<2.1ps PPJ<14ps, Eye diagram margin>24%. So it has reached the design requirements with good performance.