The Research And Simulation Of The Key Technology Of3G-BERT System Based On FPGA

By the end of2008, the mobile communication technology has stepped into the new eraof3G (3rd-generation), whose service can transmit voice and data informationsimultaneously with a rate at least hundreds of kilobytes per second. Additionally, theconstruction and operation of the mobile communication network are mainly for itsreliability. By the way, building a base station occupies for about78%of the total cost. Thetesting equipments of the excellent equipment performance and the complete correspondingperformance have become the core factor to guarantee reliability. So for the completion ofthe base station, its test equipments become very important. At present there are two kinds of3G network interface agreement standards: OBSAI and CPRI.The Agilent has alreadydeveloped the base station BERT based on OBSAI interface standard. On other hand, thebase station of CPRI interface standard is still need breakthrough and there is still a blank inthe market. According to the situation, in this thesis a design of high-speed BERT based onFPGA will be built and focused on the technologies of the system, used to test base station ofCPRI interface standard. As a preliminary exploration, in the research the rate of614.4Mbps,the lowest rate of the CPRI standard, will be applied.According to the current datatransmission standard of3G network, this thesis designs a high speed BERT based on FPGAfor the CPRI interface’s BER of3G base station. The BERT can work under both suspensionand communication modes.According to the current data transmission standard of3G network, in this thesis designof a high speed BERT based on FPGA for the CPRI interface’s BER of3G base station willbe done. The BERT can work under both suspension and communication modes. Firstly, inthis thesis a practical value of the BERT is displayed by providing an overview of the3Gnetwork’s present situation. Secondly, it defines the frame format in the CPRI standard as thedesign reference to the signal generating module under suspension mode and the signalrecovery module under communication mode. Thirdly, it builds a BERT system under thesuspension mode, with key points of the signal generating module generating PN code andthe8b/10b encoding module for simulating the communicated signal, and introduces thereceiving system including the modules of8b10b decoding, frame synchronization,comparison, counting and displaying. After the completing of the BERT system under the suspension mode, there is another under the communication mode. Because of the signalcoming from the communication network, the BERT doesn’t need the signal transmitter tosimulate a signal. For the signal is transmitted under the communication mode, the signaltransmitter isn’t necessary for signal simulating. However, to receive the signal in a real time,a FIFO cache is added, and when more data is required, an extra external SDRAM will beadded to store the data. The data recovery between the signal transmitter and the signalreceiver relies on the insertion of K bytes, and there is a procedure for the K byte’s insertionand test. Finally, the independent modules mentioned above are linked by a master controlmodule to implement the functions of the BERT system.