Based On The Development Of The Sfp Optical Module Bert

Bit error device is used in detecting for reliability of a communication system. It is an important instrument which can verify the data transfer quality and imitate the transfer channel. It can save a lot of time and cost in communication device developing process.In this thesis,the basic theory of this bit error device is shown including SDH, E3 and so on. At the same time, the SFP module which is used for O-E transfer is introduced and tested. Several important parts in this design are elaborated in this thesis, for example, SFP module, design of FPGA, use of MPC8260, and chips like PMC5319 and DS3170.In the design of the whole device, FPGA is used as a significant part to design the arithmetic include how to produce error bits, how to count error bits and how to load E1 frame and E2 frame in E3 frame, in this way, a lot of money could be saved and the whole device can be easier to be moved from one place to another place. At the same time, MPC8260 based on PowerPC is used as the CPU in this design. Through tornado some soft programs are designed, like setting bit error ratios and amounts and count and display error bits.According to advance SI and PI theory, the PCB of this bit error device is designed through the software called cadence allegro.At last, this device is tested. The simulate range from 10-1 to 10-7 and in a 400-second test, the difference is small than 1%. The bit error device is available for common use. But if we can replace PC monitor by LED, that will be better.