Research On Key Technologies Of High-performance Bus Interconnection On Multi-processor SoC

With the development of integrated circuit technology,the SoC (System on Chip)design methodology which based on IP-core multiplexing can achieve a complexelectronic system in a single chip is becoming the mainstream of today’s integratedcircuit design methodology. However, the increase of the IP-cores inevitably leads tothe increase of communication traffic between IP-cores, and the performance of thecommunication structure has become an important factor of MPSoC(Multi-ProcessorSoC). Therefore, how to provide a set of high performance system interconnectionsolutions to provide a transmission infrastructure between the processors on the chip hasbecome the key technology of the SoC design.Combining with the development demands of network processor which researchedand developed independently by Xidian university, the feature of the packet processingengine is explored and an on-chip bus interconnection protocol is designed in the thesis.Finally, a set of on-chip bus implementation scheme called XDBUS is realized. Thisscheme provides4~8processors connecting with shared resources on the chip, adoptsparallel, layered transmission structure, and provides a parallel command and data bus,the actual bandwidth achieved6Gbps at a frequency of200MHz.For a huge demand of on-chip communication bandwidth by the next generation ofnetwork processors, the on-chip bus interconnection scheme based on crossbar switch isalso explored and completed in this thesis.The sheme provides processing engines andshared resources for multiple parallel buses to improve the parallelism. Command busand data bus are separated. It provide a set of light, respectively arbiter for eachcommand bus, read and write bus. As a result, it can provide a variety of arbitrationalgorithm for system designers. In addition, based on the arbitration program in theindependence of arbitrator characteristics, system bus expansion becomes extremelysimple, the scalability of the network processor systems is greatly enhanced.Finally, the functional verification and performance analysis of the two businterconnection, detailed analysis of theoretical bandwidth, bus bandwidth utilization,theoretical transmission time delay are also achieved in the thesis. Simulation resultsshow that the bandwidth of the crossbar structure is more than2times of the XDBUS inthe same system scale.