Research On Buffer Management And High Speed Interconnection Technology Of Network-on-Chip For Multi-processor System-on-Chip

With the rapid development of social life and military technology, morerequirements have been put forward to high performance embedded computing.Integration of System-on-Chip is increasing driven by the advance of VLSI technology.Microprocessors, memory, IO devices and a growing number of hardware units can beintegrated in a single chip. Multi Processor System on Chip has become a majorresearch area of high performance embedded computing, which is driven by applicationrequirements and VLSI technology. With the development of MPSoC, the number ofcomponents on a single chip and their performance continue to increase, the design ofthe communication architecture plays a major role in affecting the area, performance,and energy consumption of the overall system. Network-on-chip approach wasproposed as a better solution to MPSoC interconnection. NoC approach offers betterpredictability, lower power consumption and greater scalability compared to classicalsolutions for on chip communication. It has great theoretical and practical significanceto study on the theories and design problems about on chip interconnection network inMPSoC, which will provide theory and technology foundation for design andimplementation of future high performance embedded multi-core systems.In the dissertation, in-depth study on buffer allocation, management and applyingtechnical issues is presented, including application specific buffer allocation anddynamic using or managing router buffers. These works is on the basis of problemdescription, classification and discussion of relevant issues in network on chips. A NoCsimulation and emulation platform in RTL level is provided based on the design andimplementation of major functional units. Then performance analysis and designexploration of some technical parameters are carried out using this platform. Finally,high speed inter-chip interconnect technology is researched for expansion ofYHFT-QDSP, which is a independent developed and implemented heterogeneousmulti-core system. The main contributions are listed as follows.1) A buffer allocation approach is proposed based on queuing model, which isaiming at the serious resource-constrained problem in NoC. Characterization analysisand formal description of buffer allocation in NoC router design are provided. Weestablish an analytical router model which uses M/M/1queuing system. The relevantparameters are extracted and the calculation of object function is proposed. Anapplication specific buffer allocation algorithm is implemented using the analyticalmodel. Customized buffer resource allocation can be achieved using the algorithm,according to traffic pattern of different application mapping. In contrast with thetraditional uniform buffer allocation strategy, about50%saving in buffer resources canbe achieved without and reduction in performance. The buffer resources are utilized efficiently in the system.2) A dynamically buffer allocation scheme OOMCR-DBU is proposed to solve thelow buffer utilization and eliminate various congestion, which is based on the behaviorcharacteristics analyzing of static virtual channel structure. Dynamic virtual channelarchitecture is presented using this scheme and the VLSI implementation of router withdynamic virtual channel is completed. The router can regulate the channel organizationaccording to different traffic pattern, and it provides throughput increase and latencydecrease with obvious saving of silicon area and power consumption.3) The software simulation environment in RTL level and hardware emulationplatform based on FPGA is presented. We create a network-on-chip system on the basisof the proposed dynamic virtual channel router. Performance analysis of various designparameters, such as network size, packet length, buffer size, the number of virtualchannels, routing strategy, is carried out with the latency and throughput act as theevaluation function. We can select proper parameter configuration to achieve the designobject and meet different constraints, on the basis of simulation or emulation platformand the performance analysis approach.4) A high speed interconnect scheme based on PCI Express is proposed forYHFT-QDSP, which is an embedded heterogeneous multi-core system. The technicalfeatures and application of PCI Express are analyzed. QLink-PCIE-Bridge, the protocoltransformation and routing module, is implemented aiming at the hierarchicalinterconnection architecture of YHFT-QDSP. PCI Express technique is applied toYHFT-QDSP by IP reuse and cutting. The inter-chip high speed expansion ofYHFT-QDSP is achieved and the design cycle is shortened.