Study And Implementation Of Service Oriented Heterogeneous Multi Processor System-on-Chip

The development of semiconductor manufacturing technology allows a heterogeneous Multi-Processor System-on-Chip (MPSoC) integrating multiple processor cores of various functionalities in it. Thus, heterogeneous MPSoCs can make full advantage of each core to accelerate multiple specified categories of tasks, and thereby simultaneously satisfies the requirements of embedded applications on many aspects, such as chip area, computing performance and power consumption. For the reason above, heterogeneous MPSoCs are widely applied in embedded computing domains. However, the popularity of embedded applications and the improvement of chip integration impose more significant challenges on heterogeneous MPSoC design. The challenges include:1) how to improve the flexibility of heterogeneous MPSoC hardware platform to satisfy the frequently changing requirements of embedded applications,2) how to improve the utilization efficiency of processor cores to make full use of the performance potential of MPSoCs and,3) how to formally modeling heterogeneous MPSoCs, especially accurately describing their complicated characteristics of dynamic events, so as to assist designers to verify the correctness and evaluate the performance of system hardware/software designs.This dissertation studies the above problems separately. The study and its innovative features involve:1) In order to increase the system flexibility, we combine Dynamic Partial Reconfiguration (DPR) technology with Service-Oriented heterogeneous Multi-Processor (SOMP) architecture by providing a system hardware/software designing flow, an inter-module communication interface and a parallel programming model which support DPR. The SOMP prototyping system is implemented on a Field Programmable Gate Array (FPGA) based development board, which demonstrates the correctness of our proposed designing method. Besides, for demonstrating the effectiveness of DPR, the reconfiguration overhead of the prototyping system and the resource overhead introduced by DPR are also evaluated in this dissertation.2) This dissertation extends Amdahl’s law and applies it into heterogeneous MPSoCs. According to the extension, we quantitatively analyze the impacts on system performance of different factors, such as the configuration of processor cores, the proportion of parallelizable tasks and task partitioning strategy. Then we point out the conditions in theory which will lead to the maximum system performance. The extension is of guiding significance to design optimizing of heterogeneous MPSoCs and improving the system efficiency.3) Fully revealing task level parallelism of applications is an efficient way of improving the utilization efficiency of multicore systems. To this end, the scheme for automatically parallelizing tasks is studied in this dissertation. By regarding tasks as abstract instructions, we extend instruction level scoreboarding algorithm to heterogeneous MPSoCs for the first time and propose a dynamical scheduling scheme named Task Level Scoreboarding (TLS). TLS can dynamically detect inter-task dependencies and automatically dispatch tasks to different cores to execute in parallel. Therefore, the task level parallelism of applications can be improved. TLS is implemented on the SOMP prototyping system and compared to other state-of-art dynamic scheduling schemes through experiments. The result of comparison demonstrates our proposed TLS introduces less runtime scheduling overhead.4) This dissertation models heterogeneous MPSoCs using a formal modeling language, Colored Petri Nets (CPN). Unlike previous research work, the CPN model proposed in this dissertation can describe not only static elements of a system such as processor cores, memory units and tasks, but also dynamic events during system execution which includes detecting inter-task dependencies and task dispatching. So the model can be employed to model task execution process in a system and the corresponding scheduling algorithm. Assisted by the model, designers are able to evaluate the performance of heterogeneous MPSoC hardware/software designs as early as possible. This dissertation utilizes the model to simulate the SOMP prototyping system, together with out-of-order task execution processes on it. By comparing the result of model-based simulation and actual execution of the prototyping system, we demonstrate that the proposed CPN model can accurately simulate the execution of heterogeneous MPSoCs.