The Research And Application Of Power Model For Interconnection Network In MPSoC

With the rapid development of the semiconductor technology, enormous transistors available on a single chip allows designers to integrate dozens of processing elements together to satisfy the increasing demand for computing and processing. Due to the advantages of power-efficiency, communication performance, reusable architecture and advanced solution for the physical problem in deep submicron technology, Network-on-Chip turns out an outstanding interconnection structure for multiprocessor system-on-chip.Due to battery lifetime, the mobility of portable devices, cooling, and thermal budgets, the methods for reducing the power consumption efficiently have been a hot issue in multi-processor design. Indeed, several multi-processor prototypes show the interconnection network takes a substantial portion of system power. Consequently, the research on interconnection network power is significant to MPSoC design.This thesis focuses on the interconnection network power optimization, and a lot of elaborated analysis and research were completed. First, a power model of interconnection network in MPSoC was proposed, and then the energy performance of input FIFO, crossbar, arbiter, link and balanced H-tree clock network were analyzed. Energy-aware task mapping methodology for Network-on-Chip was also described in terms of system-level power optimization. In order to improve the flexibility of power estimation, two simulation solutions are put forwarded. One adopts power model and the other adopts both power model and EDA Tools. Finally, the effect of network parameters and switch structure on the energy performance was explored. The simulation results are benefit for making trade-off between the communication and energy performance. Additionally, the energy performances of several interconnection structures were compared. The simulation results indicated Network-on-Chip and HCR-NoC can achieve a better energy performance than their reference objects.The main achievements of this thesis are as follows. An interconnection network power model including clock tree power was improved and two simulation solutions were proposed to obtain interconnection network power performance in different network traffic cases using OPNEC-SIM.