A High Performance Sdram Controller Design And Software And Hardware Combined With Test

With the quick development of mobile communication and multimedia technology,the embedded SoC has been widely used, and its performance requirement has becomemore stringent. Performance of embedded SoC mainly depends on the core speed andthe memory bandwidth. However, with the increasing speed of core, the memorybandwidth has become the buttleneck of SoC performance. On the basis of consideringperformance, cost, power consumption and other factors, SDRAM is a good selectionfor high speed embedded systems. Therefore, the research and design of highperformance SDRAM controller are of great significance.The main object is designing a SDR/DDR SDRAM controller with high efficiencyand stability, testing its perfomace through software benchmark, and fitting into Virtex-4XC4VLX25FF668-10C FPGA. Main jobs include:Firstly, basic principles of SDRAM are introduced, as well as supportedinstructions and typical operation timing. The detailed design scheme, according to theJEDEC SDRAM specification, is introduced. Several common bus protocols andarbitration stratigies are introduced and compared, and those, which can ensurebandwidth and latency, are implemented in the design.Secondly, referencing classical general-purpose memory controlling strategy, theSDRAM controller is optimized under the framework of current SoC. The refreshoperation is excuted as soon as the SDRAM is idle．And the address mapping strategy isalso improved to take full advantage of SDRAM’S row buffer.Finally, the design is integrated into the SoC simulation platform, and functionalverification is made using Cadence NCVerilog. At the same time, preformace aremeasured. The associated FPGA prototype is also built.The result of simulation and FPGA verification demonstrates that the designreaches the expected design objective, and the controller is compatible with multipletypes of SDRAM, includes SDR and DDR. The performance evaluation based onSTREAM benchmark and DMA demonstrates that after using several optimizationstratigies, the SDRAM controller’s bandwidth has been increased by17.8%and the system’s performance has been increased by30.6%.