| The slow SDRAM accessing speed has become a bottleneck in enhancing the performance of the whole network-processor system. Thus, the accessing speed of the SDRAM controller is crucial to the whole system. This dissertation focuses on improving the performance of the SDRAM controller and enhancing the read & write speed. Two stages were taken in designing the SDRAM controller.First stage: The implementation of SDRAM controller in single-core processing architecture. In this stage, the realization of initialization, read, write, burst read, burst write, refreshing, pre-charging and mask-operation are completed in single-core system.Second stage: The implementation of SDRAM controller in multi-core shared architecture. Firstly, asynchronous FIFO is adopted for storage of instructions from multiple processors; secondly, sequential and round-robbin arbitration policy are used to ensure precisly response among different requests from multiple processors; finally, programmable address width technique is utilized to achieve the universality of SDRAM controller.Then, taking into account the impact of arbitration algorithm on the overall system performance, an optimization stratified arbitration policy, which accomplishes arbitration according to different kinds of priority level, together with time-hiding techniques are utilized to enhance memory access efficiency.This dissertation includes the work done on the design of SDRAM controller in multi-core shared system, behavior-level Verilog HDL programming and system-level functional simulation and verification. The SDRAM controller has been applied to FPGA platform and the final results show that the design can work properly with off-chip SDRAM storage. By using time-hiding technique, the memory access speed can be significantly improved up to 40%. Additionally, programmable address width technique makes this design more flexible, supporting off-chip SDRAM with different storage capacity. |
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