Design And Verification Of A SDRAM Controller Based On CoreConnect Bus

With the development of modern society,we has entered the information age. various information develops rapidly.At this time, as the amount of storage is increasing,the requirements of memory chips are increasingly higher and higer.The high speed memory chips with large capacity 、 high security have become the mainstream of the time.SDRAM(Synchronous dynamic random access memory) has become the best choice with the advantage of high integration, low power consumption, high reliability and strong processing abiliy. But SDRAM has a complex time series, in order to meet the growing demand, the SDRAM control chip comes out.Though the development of SDRAM has entered into DDR4,it has complex design and high cost,the SDRAM controller designd in my thesis is to solve this problem.This thesis chooses the programmable gate array FPGA which is widely used in the field of programmable logic device.Using Verilog language,following the top-down idea. In the thesis,I analysis the development status of the SDRAM controller design, confirm the necessity of this design. I analysis the protocols of PLB bus and DCR bus,and the fuctions,characteristics, timing requirements of SDRAM memory.According to the project requirement,I design the performance indicators,functions of the SDRAM controller, and its timing requiremens.And then I detailed the design of each modules about the SDRAM controller.Because of the timing differences between PLB bus and SDRAM memory,So the FIFO is used in the interface conversion unit.so I design Check and error correction unit after Data control cross module.I take the ECC check and Parity check to keep the safty of data storage.In order to improve the scope of use,some methods are used,such as the starting of chip select space, the end address programmable,the SDRAM ranks, logic Bank programmable.Finally,I use the model level and system level verify the SDRAM controller and finally analysis verified waveform figure.Through the analysis of waveform figure,we can send data from PLB bus to SDRAM memory in the way of single operation, four Line operation, Line 8 operation,double word operation, four words Burstoperation.My conclusion is based on a large amount of Verification data,The SDRAM controller achieve the functions that send data from PLB bus to SDRAM memory.The design is simple,and it takes less resources, has the low cost.The basic design principle can be applied to the same kind of SDRAM controller,and it is more economical for large capacity storage...