Soc Platform, Usb 2.0 Host Controller Ip Core Design And Implementation

With progresses of manufacturing process and design technology, the scale of current digital ICs increase gradually and more and more functional modules can be integrated in one chip. So SoC owns high performance and is used very widely. Obviously, a complete SoC platform will include a high-efficient and convenient port. As one of mainstream, USB 2.0 has been a standard configuration for electronics products. Therefore, it is of great importance in theory and application to research on the realization of USB2.0 host controller.At first, this paper investigates the relevant protocols of USB 2.0, including the EHCI, ULPI and the now-days the design technique of USB 2.0 Host Controller. Then, this paper introduces the hardware part of USB 2.0 HC IP in the "Digital Home Net SoC platform", particularly details the design of the Reg_stack, ULPI_Wrapper sub-modules and the verification of the IP-core in the system. This IP-core supports the USB2.0 specification; and it can be integrated in the SoC with the wishbone bus.In the functional verification of the USB 2.0 HC IP-core, there is balance in the verification efficiency and time cost. This paper doesn't adopt the traditional method: consider wring and loading the particular test vector manually and comparing the results. It fully considers the requirements of the USB 2.0 HC, such as scheduling management and transaction control that is list in the protocol, then adopts a hierarchical verification strategy based on the functional coverage rate.It studies the design specification and analyzes all the test features of the IP-core, so it summaries the set of the functions that should be verified. Then it divides all the test features into 4 groups and starts the simulation according to the hierarchical concepts:field, packet, transfer, transaction that are defined in USB 2.0.Eventually, the USB 2.0 HC IP passes in all tests of the functional verification.Then, this paper integrates the IP into the SoC platform and realizes the whole design in the Altera FPGA. The hardware and software is optimized with it. The SoC was taped out with the UMC CMOS 0.18 um. The result means that the IP-core in this paper is up to the USB2.0 specification, supports the control, bulk transfer styles and works well in SoC. At last, acoording to the deficiency of the taped-out chip, this paper introduces the work in the FPGA platform in order to improve the performance and fix the bug.At last, the IP can accomplish the bulk transfer stably and access the Mass Strorage device with SCSI command set.