Study On The Verification Of Interrupt Delay Controller And GPIO Based On SVA-Based Functional Verification Methods

As integrated circuits have been developed in the direction of So C with high performance, high integration and low power, functional verification becomes increasingly complex and important during the development. The traditional verification techniques and methods are no longer able to meet the demand for the development cycle, verification efficiency, as well as the observability, controllability and reusability of the testbench. With the rapid development of Electronic Design Automation technique, a variety of new verification techniques and methods have been explored to improve the verification efficiency and to shorten the development cycle and to develop portable verification components and environment, which made up for the shortcomings of traditional verification techniques and methods in many respects.Based on the Assertion-Based Verification Methodology, the applications of System Verilog Assertion(SVA)-based functional verification technology were studied in this dissertation. The advantages of SVA-based verification method in environment development and verification process were investigated according to SVA language and the features of this verification technique. A formal functional verification method for Interrupt Delay Controller was proposed, and the features for assertions and assumptions were compiled using SVA according to its functional specification. This testbench was designed and built by Jasper formal technology, and the verification for this module was accomplished. This method effectively shortened the development cycle and improved the verification efficiency without reduction in verification quility. In addition, an assertion coverage rate-drive verification method was designed for General-Purpose Input and Output control module based on the popular OVM verification methodology, and the OVCs of design under test were implemented based on OVM libraries. A testbench was built by the function check and coverage rate of assertion module, from which a high-level, high-coverage and strong-reusability verification environment was achieved.The functional verification of design under test was successfully accomplished by using the testbench and environment developed in this dissertation, which have found applications in actual project. The idea of IDC’s formal verification has been extended to other similar modules, and the OVCs and assertions of GPIO have been well reused in other projects. Research results and practice showed that the formal verification environment achieved by SVA-based functional verification techniques and methods effectively shortened the development cycle and improved the efficiency of verification. The OVM testbench and environment had high coverage rate and reusability with functional coverage rate of 100% and code coverage rate of 97.9%.