Research On RISC-V Instruction Set And RV32I Based Processor Core Design

At present,the architecture of general-purpose processors are mainly based on X86 architecture and ARM architecture.The X86 architecture processors which have high frequency and strong computing power,are used in servers,desktop computers,and notebook computers,while the ARM architecture processors concentrate on the high frequency and low energy consumption,and its products has larger market in mobile phone silicon-on-a-chip(SOC)and embedded devices.With the increase popularity of new areas like artificial intelligence,the Internet of Things and edge computing,the demand for low cost and low power solution is more important to these areas.Meanwhile,RISC-V architecture is very suited in these areas as it has the benefits of simplified instruction set,modularity,and the most advantageous,it is an Open Source resource.The emergence of RISC-V architecture as a popular option of processor started from the utilization by many start-up companies,but there are also many shortcomings.Firstly,there are many different implementations of RISC-V instruction set,but the procedures of implementation are not disclosed because of know-how problem;secondly,many implementations do not allow any enhancement or customization to the foundation architecture,like pipelining and multi-processor.Based on the above shortcomings,A 32-bit sequential Single Cycle Processor and a Five Stage Pipeline Processor are designed in this thesis.The processors can operate on RV32 I instruction set.The thesis can be summarized as follows.(i)Research on RV32 I instruction set and Processor microarchitecture,and design a Single Cycle Processor with8 K byte Tightly Coupled Memory.(ii)On the basis of single cycle processor design,pipeline technology is studied,and a Five Stage Pipeline Processor is designed.(iii)A bus interface is designed and a new interface protocol is defined for the processor,which realizes the core capable of accessing peripherals and peripherals capable of accessing the processor's Tightly Coupled Memory.The entire digital design of Verilog behavioral-level modeling,RTL-level description and FPGA verification are all based on the Xilinx AX7A035 development board.The verification results show that the designed single-cycle processor can support up to 28 basic instructions of the RV32 I instruction set.Running at a clock frequency of25 MHz,the core consumes a power of 1m W and the CPU consumes a power of 2m W.The total implementation occupies a total of 819 LUT units,1024 registers and 228 multiplexers of the FPGA resources.