Design And Implementation Of Double-precision 64-bit Floating-point Multiplication Unit

Studies show that the efficiency of floating-point multiplication operations directly determines the frequency of the processor (CPU), whereas the former is based on integer addition operations. Therefore, the design of an integer addition framework and a floating-point multiplication framework with higher executive efficiency is of great importance to the promotion of processor performance. Analyzed are the current integer adder algorithms, including the algorithms of ripple carry adder, of carry look-ahead adder, and of carry select adder, etc., proposed is the Barrel Integer Adder Algorithm, a half-adder-based algorithm for integer adder, focusing on the basic principles of the algorithm and a detailed analysis of its algorithmic time and area of complexity. In the simulation validation of the algorithm with FPGA, the traditional integer adder and the Barrel Integer Adder are analytically compared in terms of speed and area, the results of which prove that the latter can run faster, and in addition, can be more advantageous in high digit addition. This provides for a good foundation for the design of floating-point multiplier. In connection with floating-point multiplication algorithm, proposed is the application of Vedic multiplication to the design of binary integer multiplication on the basis of research in ancient Indian Vedic multiplication, described in detail is the process of Vedic binary integer multiplication, and introduced is the Barrel Adder to speed up the process in partial product compression and the final stage of summation. For IEEE-754 Floating-Point Format Standard, proposed is a project for the realization of double precision floating-point multiplication operations based on Vedic algorithm. The design of the computing unit is completed with VerilogHDL Hardware Description Language, and is combined with Avalon Internet Framework and Nios II Processor by using SOPC Builder Tools, the entire system of which is realized on the bases of Cyclone FPGA Hardware Platform. Simultaneously, carried out are the modular tests and overall verifications of the computing modules, with which the correctness of the program is proven to have reached not only its design requirements, but also faster speed, and therefore, achieved a very good practicality.