Implementation Of RISC-V Floating Point Instructions Based On ShenWei Architecture

Based on the in-depth analysis of the instruction format and instruction function of RISC-V floating-point instruction set,this article implements the corresponding floating-point instruction function under the RISC-V based on the functional design of the Shenwei core architecture for the floating-point instruction in RISC-V.The implemented RISC-V floating-point instructions use instruction multi-issue technology.Compared to single-issue instructions,multiple-issue instructions can be executed in parallel at the same stage,effectively improving the utilization of functional components;According to the out-of-order processing strategy,an issue module capable of transmitting multiple RISC-V floating-point instructions in the same cycle is realized.The issue module mainly consists of a ready queue,a scoreboard,and an issue queue.Each part adopts the corresponding arbitration mechanism,wake-up mechanism and corresponding entry update mechanism,the multi-issue control from the instruction issue module to the instruction execution unit is completed.This article delves into the structure of floating-point components and its implementation.Based on the RV32 F and RV32 D floating-point instruction sets in RISC-V,a floating-point arithmetic unit(FPU)that supports single / double-precision floating-point operations are implemented.The floating-point multiply-add operations and floating-point add / subtract / multiply operations are implemented in the floating-point fusion multiply-add(FMA)component.The FMA unit is implemented in a 6-stage pipeline mode.In addition,the main adder of the FMA part uses an End-Arround-Carry(EAC)adder,and the adder is optimized for design.By reducing the EAC logic width,the area and power consumption of the adder are reduced,where the area is reduced by about 27.0% and the power consumption is reduced by about 24.7%.In addition,the adder can avoid the complement operation for negative numbers,reduce the delay and improve the execution efficiency.In addition,the execution of the floating-point comparison instruction is optimized,and the execution result of the floating-point comparison instruction is changed from the original 6-cycle delay optimization to 2 cycles,and the operation delay is reduced by 4 cycles.At the same time,according to the characteristics of RISC-V floating-point arithmetic instructions,the rounding mode of an instruction can be directly changed through the static rounding mode bit,which effectively improves the performance.Finally,a floating-point instruction test platform was set up,and a large number of test incentives were used to complete the verification of the multi-issue execution instruction implemented in this paper.The timing simulation of RISC-V floating-point instructions is implemented,and the simulation results show that the RISC-V floating-point instructions designed and implemented meet the design requirements.