Implementation And Optimization Of High-Performance Floating-Point Unit In X Processor

FPU is one of the key units which determines high-performance microprocessor performance. A floating-point adder unit and a floating-point issue queue are implemented in superscalar X processor, and the corresponding structure of the processor was improved in this thesis. The corresponding functional verification and the performance test show that the design features of the floating-point units can be correctly implemented. The improved performance of the floating-point units was effectively increased in specific applications. Research content and related conclusion of this thesis was directly used for engineering application. Including:Implement a Focused- Distributed Issue Queue structure in this thesis. By the analysis of the high-performance floating-point issue queue, the focused-distributed issue queue structure was implemented. The issue queue was conponent of issue block,select block and scoreboard block. With the implemention of the appropriate wake algorithm, arbitration algorithm and update algorithm, the issue queue completed instruction issue. Then, the way based on the function point-driven was used for function verification. Function point coverage was used to ensure the validity and reliability of the design. The floating-point code coverage was get by setting the function point and the observation point to ensure correct function of the issue queue.Implement a floating-point adder unit of polymerization structure in this thesis.A dual-channel floating point adder structure is made as the basic framework, by resource sharing principle, which means the operations of floating-point and fixed-point,floating point and integer of floating-point, single-double precision floating-point and half-precision floating-point are fully integrated in dual-channel floating-point adder, a floating-point adder of polymeric structure was implemented. The floating-point adder of polymeric structure makes effective use of hardware resources, meanwhile it reduces the corresponding implementation area. The way based on large-scale random numbers-driven is used for function verification. Code coverage drives the entire verification process. Code coverage is used to detect and assess the quality of verification work.Firstly, implement an improved Focused- Distributed Floating-point issue queue with dual input port structure in this thesis. The structure can be supported effective double the receiving width of issue queue by increasing the issue queue of the input port.In this structure, a virtual reservation station issue block type is applied. Secondly, the number of issue queues is increased from 8 to 16, which improve the efficiency of the issue of floating-point instructions effectively. Test results show that improved issue queue can improve the efficiency of execution of floating point instructions effectively.And the performance of the improved issue queue is increased by 3.4%.Implement an improved low latency, high performance floating point adder separate parts of the structure in this thesis. Floating point adder of polymeric structure can save area,but it does not meet the performance requirements of the ultra-high-performance floating-point processor. By stripping the floating-point conversion from the floating-point adder of polymer structure, using based on the physical synthesis guiding optimization iterative method, the delay of floating point adder is reduced to 3from 4, so theoretical performance is increased by 25%. Conversion class instruction delay is reduced to 2 from 4, so theoretical performance is increased by 50%. Actual performance tests show that the performance of improved floating-point unit can meet the floating-point performance requirements of the X processor for ultra-high performance. Actual performance is increased by 3.7%.