| Convolutional neural network has been extensively studied and applied in the field of machine vision,and field programmable gate array(FPGA)can carry out hardware acceleration design of convolutional neural network algorithm,which can utilize the parallel processing ability of FPGA to improve the efficiency of data operation.In this paper,the object detection of convolutional neural network is taken as the research objective and developed on the FPGA hardware platform.In order to improve the operational efficiency of convolutional neural network algorithm and reduce the power consumption,the hardware acceleration design of convolutional neural network algorithm and the recognition and detection of handwritten digits in the target image are studied.In this paper,by learning the basic knowledge of convolutional neural network,master the principle and function of each level,optimize and improve the Le Net5 model structure,construct the MF＿Le Net network,and conduct training,using the same data set for the same number of training,compare and analyze the detection accuracy of the two models;Based on the analysis of the hardware acceleration structure,the parallelism of the main levels in the convolutional neural network is studied.Combined with the characteristics of the levels,the realization of the hardware platform is considered comprehensively,and the appropriate parallel series is designed for the purpose of reducing resource consumption.In this paper,hardware and software are used to complete the overall design.The software part mainly obtains the weight data and bias,and the hardware part realizes the hardware acceleration and optimization design of MF＿Le Net network.In the part of hardware acceleration,functional modules are divided to complete the hardware design of the convolution layer,pooling layer and fully connected layer.The optimization and acceleration of the data flow are completed by means of parallel structure optimization,parameter localization,data reuse,module reuse,pipeline control and other methods of the data flow.The data flow method of the top-level module algorithm runs through a single module to complete the design of the hardware system.The constructed convolutional neural network algorithm is tested at the board level.According to the detection results,the accuracy of model detection of the FPGAbased CNN target detection system in this design is 98.5% under the same data set and the same number of training,which is better than the accuracy of Le Net5 model of98.3%.The detection time of an image is 27.531 us,and the power consumption is1.735 W,which is only 2.3% and 1.6% of the CPU and GPU power consumption,and the resource consumption accounts for 40% of the total resources. |
