Design Of Convolutional Neural Network Acceleration Based On FPGA

Convolutional neural network is a kind of deep learning algorithm,which has achieved great success in the field of computer vision.With the enhancement of convolutional neural network functions,the complexity of the model is also increasing,which makes it difficult to apply the convolutional neural network to some devices with limited computing resources,storage resources and power.FPGA is a product developed further on the basis of traditional programmable devices.With its high energy efficiency ratio,high parallelism,and reconfigurability,it is rapidly becoming the preferred platform for accelerating the inference stage of convolutional neural networks.This thesis proposes a convolutional neural network parallel acceleration architecture based on ARM+FPGA,and integrates the Winograd fast convolution algorithm to replace the traditional convolution algorithm,which accelerates the forward calculation of the convolutional neural network.The main research contents of this thesis are as follows:(1)An ARM+FPGA-based convolutional neural network parallel acceleration architecture is designed,and an effective parallel computing strategy and data flow design are proposed.The feature map data and weight data are calculated in blocks by using the block-based computing mode.Based on a data reuse method,the actual utilization rate of on-chip cache data is improved effectively.A new type of ping-pong buffer is designed to cover the computation delay and transmission delay and reduce the delay effectively.(2)Winograd fast convolution algorithm is used to replace the traditional convolution algorithm,so that the multiplication operation of convolution operation is replaced by addition and shift operation,which reduces the computational complexity of network forward calculation and reduces the use of DSP resources.Combined with the characteristics of FPGA,an improved Winograd algorithm is proposed,and the whole calculation process is pipelined.At the same time,the calculation data needed in Winograd algorithm is quantified with low precision.According to the different distribution intervals of weight parameters of different convolutional layers,the 32-bit floating point parameters are converted to 16-bit dynamic fixed-point format,which reduces the resource consumption and improves the calculation efficiency.The simulation verification is completed in Linux.(3)According to the proposed architecture design,perform mathematical modeling and quantitative analysis of performance and resource usage.The experimental results are compared with the predicted results.Compared with other methods,it’s proved that the architecture proposed in this thesis can effectively improve the speed of forward calculation.