| Millimeter wave has abundant spectrum resources and is a research hotspot in the wireless communication field.Especially,research on high-speed wireless transmission technology based on E-band(71～76 GHz,81～86 GHz)has become an important foundation to support the development of future communication networks,because it has low atmospheric attenuation.In millimeter wave communication system,synchronization is a crucial component in baseband signal processing,and the performance of synchronization algorithm will directly influence whether the system can correctly recover transmitted data.It is particularly important to design and implement the synchronization algorithm reasonably as we consider the larger bandwidth and higher transmission rate.In this thesis,a low complexity frame synchronization and carrier synchronization scheme is proposed for E-band millimeter wave communication system with single-carrier and dualpolarization architecture.In frame synchronization,coarse synchronization combined with fine synchronization is employed,in which joint coarse synchronization is performed after data superposition of dual polarization channels,and fine synchronization is performed separately.The low complexity scheme of the classical algorithm is given;In carrier synchronization,based on frame synchronization process and frame transmission characteristics,a fine carrier frequency offset estimation algorithm based on phase difference between frames is proposed,which can achieve more than 2 d B improvement compared with the S&C algorithm and cross correlation algorithm.Based on the characteristics of dual-polarized transmission of the system,a specific frequency offset and phase offset estimation and compensation scheme is given.The sampling rate of the system is 4.8 GSPS,and the baseband part needs real-time processing of the sampled data of the two polarization channels.To meet the requirements of high-speed parallel processing,in this thesis,the synchronization algorithm is implemented in parallel on the FPGA.The parallelism of coarse synchronization is 16,and the parallelism of fine synchronization is 8.The carrier synchronization and cache management are also implemented in the synchronization module.Simulation test showed that the hardware circuit functions meet the design expectations.After synthesis the hardware circuit under 300 MHz,resource consumption and timing of the synchronization module is verified to meet the design requirements.The board-level test of synchronization module is completed in the Baseband loopback link,and the synchronization module is able to function properly. |
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