| Since the development of semiconductor circuits,various technologies have matured,and Moore’s Law,which explains its development law,has gradually taken root in the hearts of the people.However,the feature size of CMOS has gradually approached the physical limit,and in this case,it is confusing whether to continue to obey Moore’s Law.Therefore,the search for emerging technologies as an important alternative to traditional CMOS technology has become a research hotspot,and superconducting electronics technology is one of the optimal solutions of the alternatives.With its unique advantages of high speed,low power consumption and quantized information storage form,superconducting SFQ circuit has become the world’s mainstream superconducting electronic technology.But it also has the drawback,namely the lack of large-scale memory.At present,the mainstream implementation methods are roughly divided into two categories,one is to form a memory through the Josephson circuit,but due to the low integration and low driving ability of the Josephson circuit,it is difficult to build a largescale,high-density cryogenic memory using only superconducting technology.Another way to achieve large-scale superconducting memory is to use Josephson-CMOS hybrid circuits,which not only have the characteristics of high frequency and low power consumption of superconducting SFQ circuits,but also take advantage of the mature process and stable performance of CMOS circuits.Using the existing mature CMOS manufacturing process to make memory,it can initially meet the working needs of largescale SFQ digital systems.At present,there are mainly two superconducting interface circuit structures,one is the SQUID circuit;The other is the use of JLD circuits.In this Thesis,the JLD-type interface circuit is optimized and the 4JL circuit is used as the preamplifier circuit to form a two-stage interface circuit.A series of tests were carried out using a two-stage interface circuit.In the single-chip test,the interface circuit can amplify the input of about 0.2m V to 40 m V,the bias range is ±18.6%,and it can ensure that any 18 channels in the 21 channels work at the same time without interference;In the joint debugging test,the joint debugging test with the superconducting CPU and the joint debugging test with the semiconductor amplifier were completed successively,and the signal transmission ability of the two-stage interface circuit was verified.Finally,the four-chip joint debugging test was preliminarily completed in the system joint debugging,and the signals of ten channels were successfully transmitted,and the data reading and writing experiments were realized.However,in the joint debugging test,the two-stage interface circuit exposed high bit error rate,small bias range,and insufficient sensitivity to small input currents.Therefore,a DC-SQUID circuit using mutual inductance structure as input is designed,which is used as the input of the two-stage interface circuit,which further improves the interface circuit’s ability to identify small input currents.The resulting interface circuit has a low bit error rate of 10-9 over a bias range of ±30.8% driven by an input current of 67Α,operating at 5GHz. |
