Adaptive Predistortion Based On Polyinomial Structure

In the information age of the Internet of Everything,in order to obtain higher data transmission efficiency,mobile communication systems continue to develop in the direction of large bandwidth and low latency.At the same time,in order to obtain better spectrum utilization,a large number of non-constant envelope high-order modulation techniques are adopted.These characteristics pose great challenges to wireless transmitters.On the one hand,under the excitation of large bandwidth signals,RF power amplifiers inevitably exhibit complex nonlinear behaviors including deep memory effects.On the other hand,the channel distortion characteristics of the transmitter itself will become more obvious and interact with the nonlinearity of the power amplifier,which will further damage the communication bit error rate.At present,the widely used digital predistortion is generally based on the low-speed system implemented on heterogeneous platforms,which has high cost and is weak in low-latency scenarios.In view of the above problems,the main work and innovations of this thesis are as follows :(1)In this thesis,the polynomial model of broadband power amplifier is studied.Based on the analysis of the basis function,calculation accuracy and complexity of the polynomial model,it is pointed out that the model faces the balance between calculation accuracy and complexity in the actual communication system,and an S-CMP model with low complexity is proposed.Combined with the iterative structure to optimize the polynomial transfer array,a reconfigurable S-CMP predistorter is implemented based on the FPGA platform.The model accuracy test of the power amplifier under the excitation of 100 MHz bandwidth signal is carried out.It is verified that when the nonlinear order is 9 and the memory depth is 3,compared with MP,1-DDR and other models,the NMSE is increased by 5.28 d B and 2.77 d B respectively,and the complexity is only 40 % while maintaining the accuracy of the GMP model.(2)In this thesis,the predistortion parameter identification algorithm is studied.The key factors such as hardware implementation complexity and convergence performance of the existing algorithms are analyzed.In order to overcome the low parallelism of the traditional implementation structure logic of the RLS algorithm,the two-dimensional streaming directional propagation network optimization is introduced to improve the computational efficiency of the algorithm.Then,the design and implementation of highspeed RLS parameter learning engine is completed based on FPGA platform.Through comparative tests,the scheme implemented in this thesis greatly improves the computational efficiency.For example,when the number of RLS filter taps is 14,the computational time consumption is only about 2.02 % of the ARM scheme,and with the increase of the computational complexity of the algorithm,the scheme in this thesis improves the computational efficiency more.(3)In this thesis,the hardware deployment scheme of adaptive predistortion system is studied.Firstly,a predistortion feature extraction platform based on RFSOC is built,and the channel distortion problem is tested and theoretically analyzed.A correction scheme of step-by-step time-domain filtering is given.After testing,the EVM of the245.76 MHz bandwidth excitation signal before and after correction is 5.4277 % and1.9028 % respectively.Secondly,on the basis of S-CMP predistorter and RLS parameter learning engine,the adaptive predistortion system is improved by combining the key design of predistortion delay searcher,and successfully deployed on the aforementioned RFSo C platform.The system test results show that the ACPR of the power amplifier output signal is corrected to-50.3016 /-50.6311 d B and-46.4339 /-44.5353 d B respectively under the excitation of 40 MHz and 80 MHz bandwidth excitation signals.