Research And Implementation Of Digital Predistortion (DPD) Algorithm For Radio Frequency Power Amplifier

With the rapid development of science and technology,the requirements of wireless communication technology are becoming more and more strict.The premise of high-quality signal transmission is that the wireless communication system must have high data transmission rate and rich spectrum resources.However,the memory effect and nonlinear characteristics of RF power amplifiers will cause out-of-band spectrum expansion of transmitted signals and reduce the utilization rate of spectrum resources,that is,the greater the degree of nonlinear distortion,the lower the utilization rate of spectrum and the worse the communication quality.Linearization is a common method to correct power amplifier nonlinearity in contemporary communication systems.Among many methods,digital predistortion(DPD)becomes the most popular linearization technology because of its easy realization,low cost and obvious effect.This paper mainly studies the digital predistortion identification algorithm to reduce the complexity of digital predistortion technology and improve the performance.To address the problem of poor tracking ability of traditional recursive least squares(RLS),a variable forgetting factor NVFFRLS digital predistortion identification algorithm is proposed,combining indirect learning structure with memory polynomial predistorter model(MP)for simulation experiments,and the simulation results show that the NVFFRLS algorithm has faster convergence of estimation error,smaller error values,and better linearization than the traditional RLS algorithm.The maximum improvement of ACPR and EVM value of the predistortion system based on NVFFRLS algorithm is2.46 d B and 0.9258%.The traditional RLS algorithm is widely used as a digital predistortion identification algorithm because of its superior convergence speed.However,its arithmetic complexity reaches O(N~2)(N is the size of the system),which brings challenges to hardware implementation.Moreover,many algorithms introducing variable forgetting factors only increase the difficulty of hardware implementation.Therefore,this paper proposes to use DCDRLS algorithm with low complexity and slightly lower convergence speed than RLS algorithm to identify digital predistorter parameters,where the complexity of DCDRLS algorithm is O(N)level.In the same way,a low complexity VFFDCDRLS digital predistortion identification algorithm is proposed by introducing variable forgetting factor again on the basis of DCDRLS algorithm and experimental simulation is carried out.Simulation results show that under the same number of successful iterations,compared with the DCDRLS algorithm,the digital predistortion modeling accuracy of this algorithm is higher,the linearization effect is better,and the ability to inhibit the out-of-band spectrum expansion is stronger.When the number of successful iterations is 50-150,the ACPR value of the upper and lower sideband is reduced by about 4 d B at most.When the number of successful iterations is 200,the performance index of VFFDCDRLS algorithm is closest to RLS algorithm,and the upper and lower sideband ACPR of DCDRLS algorithm is reduced by 1.64d B and 1.37 d B,respectively,and the NMSE value is reduced by 1.98 d B.On the premise of saving storage resources and arithmetic logic resources,the paper designs a module based on FPGA matrix,vector multiplication module,delay alignment module,complex multiplication module and maximum location module,and uses the key modules to build the top module of baseband digital predistorter based on DCDRLS algorithm.The whole design process only occupies 13%of the logical register resources.It provides storage resource support for future optimization of DPD.