| Compared with conventional radars,multi-beam phased array radars have better performance and higher reliability,so they are more widely used in practical applications.However,the multi-beam phased array radar generally has a larger amount of data,more complex algorithms,and higher requirements for hardware platform resources and real-time performance.Combined with a ground reconnaissance multi-beam phased array radar project,this paper uses FPGA and multi-core DSP architecture to process multiple received beam data,and discusses in detail the design and implementation of related algorithms based on multi-core DSP.The main work of this paper is as follows:1)Design,analysis and simulation of radar signal processing algorithm based on DSP.The DSP needs to receive the multi-beam data compressed by the FPGA pulse through the SRIO high-speed serial port,and perform processing such as moving target detection,constant false alarm detection,target condensation and angle measurement.The moving target detection is analyzed and simulated.The traditional three average-type CFAR algorithms are compared,namely,the cell-average constant false alarm,the smallest of constant false alarm rate,and the greatest of constant false alarm,It is pointed out that they have clutter edges effect and target shadowing,gave and simulated the ordered statistical constant false alarm method to effectively solve these two problems.Compared the conventional target agglomeration method and the connected domain target agglomeration method,pointed out and verified by simulation that the latter can avoid the target splitting phenomenon when the former is condensed.The multi-beam forming and single-pulse sum-difference ratio angle measurement are analyzed and simulated,and the corresponding angle detection curve is obtained.2)Interface design,debugging and testing.According to the requirement of data transmission between DSP and FPGA and between DSP and upper computer,the communication scheme of internal and external interface of the system is designed.The software programming related to SRIO,GPIO and Gigabit Ethernet ports is discussed,and the corresponding communication tests are verified.The results show that the transmission rate of SRIO is 11.248 Gbps,which meets the design requirements of 1.289 Gbps,and the transmission rate of the Gigabit Ethernet port is 592 Mbps,which meets the design requirements of 243.75 Kbps.3)DSP multi-core task allocation,synchronous communication,resource optimization and real-time processing.A signal processing implementation scheme of multi-core ping-pong pipeline operation based on real-time operating system SYS/BIOS is presented.EDMA is used to move the data on DDR3 to L2 for processing to save time;IPC is used to realize multi-core synchronization;Message Q mechanism is used for inter-core communication,and the cache consistency problem is solved.In multi-core resource allocation,maximize the utilization of L2 SRAM.Experiments show that the signal processing of a CPI data can be completed in real time within 256 ms,and the target information is reported to the upper computer.4)Debugging and test verification of radar signal processing system.Using the simulated radar echo,the DSP initialization,EDMA and signal processing algorithms were debugged,the correctness of the target information received by the host computer was verified.The experimental scheme of using vector signal source to simulate radar target echo is further discussed.The experimental results show the correctness,stability and real-time performance of the whole radar signal processing system. |
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