| With the continuous development of network technology and the continuous improvement of network bandwidth,the high-speed processing of large-bandwidth network data packets in cloud data centers consumes a lot of host processor resources.The services provided by cloud data centers are diverse and constantly changing,which requires flexible processing of network packets.By carrying a processor core,SmartNIC can buffer and process data packets while transmitting data packets,which alleviates the problem that processing network data packets occupies too many host processor resources.Compared with the non-open source ARM instruction set architecture,the open RISC-Ⅴ instruction set architecture that appeared in recent years has the characteristics of simple instructions and good modularization.However,the application of this new instruction set architecture on SmartNIC has not been fully studied.This thesis proposes a new SmartNIC design scheme based on RISC-Ⅴ.The design of the SmartNIC adopts a scheme of sending and receiving circular queues,which realizes the bidirectional high-speed transmission of network data packets.The open source,lightweight PicoRV32 RISC-Ⅴ processor core provides programmability for the SmartNIC,which can dynamically process network packets during transmission.By dynamically loading the RISC-Ⅴ program during the operation of the SmartNIC,the usage scenarios of the SmartNIC can be flexibly adjusted.In the design of SmartNIC,a UART controller is added to realize the printout of PicoRV32 debug information,and GPIO controllers are added to read IO input and send IO requests.The RISC-Ⅴ-based SmartNIC is implemented on the Xilinx Alveo U280 FPGA board,and its programmability and performance are tested through application examples in several typical scenarios.In 100 Gbps network environment,a single RISC-Ⅴ processor core can achieve high network performance while providing good programmability for SmartNIC(a bandwidth of 21Gbps). |
