| In recent years,with the development of the information society,driven by technologies such as artificial intelligence and big data,people’s demand for high-speed processing of information has grown exponentially.In order to meet the requirements of communication systems in modern society for high resolution,high bandwidth and high sampling rate,optical analog-to-digital converters emerged as the times require.Among the various optical analog-to-digital conversion schemes reported so far,the all-optical analog-to-digital conversion scheme based on phase-shift optical quantization has the advantages of simple structure and great integration potential,and is one of the important directions for the development of optical analog-to-digital converters in the future.In order to process the high-speed and large-capacity data stream brought by the high sampling rate of the optical analog-to-digital converter,the back-end circuit of the optical analog-to-digital converter must have the ability to process high-speed and large amounts of data in real time.This paper focuses on the cascaded multimode interference coupler phase-shifting optical quantization optical analog-to-digital converter scheme proposed by the laboratory group,and designs the back-end data receiving and processing system based on the field programmable logic gate array.The main work content of this paper is as follows:1.According to the back-end circuit of the optical analog-to-digital converter,the framework of the back-end circuit program system is designed.Starting from the function,the program system is divided into two parts:the back-end circuit board driver and data processing.It expounds in detail the three logics that need to be realized within the FPGA:high-speed data reception,back-end circuit board chip driver configuration,and data processing.In order to realize the control of the back-end circuit board chip,a back-end circuit board drive system with MircroBlaze as the core and SPI protocol and IIC protocol as the main control protocols is designed.It is connected with the upper PC through the UART protocol,and the back-end program system control communication protocol is formulated based on the UART protocol.The upper computer PC uses this communication protocol to realize real-time control of the back-end program system,including the configuration of the back-end circuit board,Data receiving control,data processing algorithm control,etc.2.In the high-speed data receiving process,the gigabit transceiver is used as an interface to receive high-speed serial data from the electrical ADC.Due to the phase difference of different channel data,the data will be out of sync,and the data collected by the electrical ADC is scrambled with pseudo-random binary sequences.Therefore,a data synchronization descrambling algorithm is designed based on PRBS,realizing the two functions of data synchronization and descrambling.In addition,in order to ensure the accuracy of the sampling data of the ADC chip,a data correction algorithm is designed to control the sampling time of the electronic ADC chip through the delay line chip,so that the electronic ADC collects data at the peak point of the pulse,thereby improving the accuracy and stability of the collected data.Finally,through the board experiment,it is confirmed that the back-end program system can realize the expected function,and the data synchronization and descrambling algorithm realizes the data synchronization and descrambling between the electronic ADC chip and the chip.Under the condition that the FPGA execution frequency is 156.25Hz and the buffer area width is 1024 bits,the average execution time of the synchronization algorithm is about 217.1 us,and the maximum skew can be corrected for 992 clock cycles.The data correction algorithm enables the electronic ADC chip to collect data near the peak point of the pulse,and the delay line chip delay controls the sampling time of the electronic ADC,and its accuracy can reach 1ps. |
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