Research On Real-time Analysis Methods For FPGA Neural Network Accelerators

With the rapid development of artificial intelligence in the field of real-time,convolutional neural networks(CNN)are widely used in the field of real-time.With the increasing amount of data on the network model,the traditional embedded system can no longer provide the performance required by the CNN network model.The neural network accelerator based on the heterogeneous embedded computing platform is the best way to solve this problem.The DPU(Deep Learning Process Unit)in the Xilinx Vitis AI toolchain is an FPGA-based neural network accelerator for accelerating convolutional neural network inference on Xilinx FPGA devices,and it has become one of the most mature FPGA neural network accelerators used.For the design of real-time embedded systems including autonomous driving,static analysis of the WCET(Worst-case execution time)bound of the programs that need to run on the system is essential before design.In this work,the FPGA system on chip under single DPU environment is analyzed and modeled,WCET analysis is conducted,and memory access behavior is analyzed.The WCET bound of a complete CNN inference is estimated by the analysis method proposed in this paper to be nearly 46%(up to 98%)better than the most advanced results at present.Then,we show that in a multi-DPU environment,the observed worst-case inference time for a CNN inference task could become 3X larger w.r.t.the best-case inference time,which prompts the prominent importance of a static WCET analysis for FPGA-based CNN inference.So,we propose a static timing analysis framework for CNN inference in a multi-DPU environment,based on a generalized timing behavior model for shared bus arbitration and memory access contention between parallel running DPU engines,this is the first WCET analysis framework for CNN inference in a multi-DPU environment.Based on the proposed WCET analysis method in this study,this research validates the feasibility of providing various DPU configuration methods for a given neural network model.DPU architecture,and FPGA system architecture.The method contributes to the estimation of system performance and facilitates the selection of optimal configuration schemes to prevent excessive resource allocation.These findings hold significant implications for improving system design methodologies and enhancing overall efficiency and effectiveness in resource utilization.