Design And Implementation Of Parallel Multi-access Memory Interface

In a Multi-Processors System-on-Chip (MPSoC), data exchange frequently between on-chip processors and off-chip shared memory. Network-on-chip (NoC) technology provides the conditions for parallel computing and memory access of on-chip processors. Higher bandwidth utilization of memory interface is needed urgently by parallel multi-tasks in MPSoC. Traditional simple memory interface cannot take full advantage of the bandwidth of off-chip memory to meet the needs of parallel memory access. Referring to the multi-processes time-shared algorithm of CPU, this paper discusses a parallel multi-access technique on user side which applies to MPSoC. The technique utilizes the bandwidth distinction between both sides of the memory interface and time slice concept to achieve time-shared exclusive operation on SDRAM side and parallel operations on user side. With above studies, this paper designs and implements a kind of parallel Multi-Access Memory Interface (MAMI) to make full use of the bandwidth of memory and improve the performance of the target system.The main work is as follows:1. Referring to the parallel operations of multi-tasks using time slices in a time-sharing system, this paper analyzes the principles and presents the design scheme of MAMI. It discusses the selection of the working mechanisms and key parameters, such as the mechanisms of arbitration and time slice switching, the size of time slices and so on.2. This paper designs the MAMI hardware prototype and implements it on FPGA according to the design scheme. The mechanism of self-inquiry and allocation of data ports is added to allocate data ports automatically in order to solve the problem of data ports allocation in parallel memory access. The time slice round-robin mechanism is optimized to hide the data channels switching time to achieve seamless switching on SDRAM side. The MAMI has two operating modes:the configuration mode and the self-inquiry mode. The configuration mode supports all tasks of the target system. The self-inquiry mode eliminates a lot of preparatory work of data ports allocation for programmers.3. This paper integrates the MAMI design into the target system to replace the original memory interface only supporting one read and one write memory access operation. By mapping tasks with different ratio between calculation and memory access, this paper discusses the influence of Data Transmission Parallelism (DTP) and performance of system tasks brought by MAMI design. Based on the compute-intensive and data-intensive applications, the Range Doppler (RD) algorithm is mapped into the target system integrated with MAMI design. The performance analysis results are given to guide the algorithm mapping work. The results show that, on the Xilinx Virtex6 1x760 ff1760-1 FPGA chip, the system integrated with two modes of MAMI achieves improvements of 17.79% and 18.13% in sub-aperture calculating,6.39% and 6.83% in synthetic aperture calculating,8.87% and 9.21% in a sub-graph with increasing almost 3% in Slice Registers, 2% in Slice LUTs,4% in Block RAM/FIFO hardware resource consumption, compared with the system integrated with one read and one write memory interface. The performance of massive matrix transpose task is improved obviously. Above all, the MAMI design meets the requirements of system and achieves high performance.