Design And Implementation Of Parallel SM4 Encryption System Based On FPG

At present,with the rapid development of industrial Internet of Things and network communication,the importance of information security has become increasingly prominent.SM4 and AES encryption algorithms can protect citizens’ privacy and network-related data.However,at present,the SM4 and AES modules in the encryption chip are mostly implemented independently,and the hardware resources are excessively occupied,which can not meet the requirements of different users for cryptographic algorithms in different environments.Moreover,in the face of the increasingly huge amount of information,the speed and throughput of a single encrypted IP core when processing multiple groups of data are limited.Therefore,this paper designs a parallel encryption system compatible with SM4 and AES encryption functions,and puts forward the following solutions:Aiming at the limited application scenario of independent encryption algorithm.In this paper,the principle of SM4 and AES algorithm is studied,a hardware fusion design scheme is proposed,and an encrypted IP core with SM4 and AES algorithm fusion is realized.The fusion scheme is as follows:(1)The sub-operation layer designs a key expansion and a round function encryption state machine to realize the fusion of the bottom modules.(2)The control layer designs a functional processor to realize the analysis and processing of plaintext,ciphertext and flag bit signals.(3)In the interface layer,SM4 and AES IP cores share the I/O interface to realize the integration of the two algorithms.Aiming at the problem of limited data processing speed of a single encrypted IP core.The following optimization schemes are proposed:(1)The pipeline controller is designed inside the converged IP core.After optimization,the encryption time of SM4 function end is saved by 15.2%,and that of AES function end is saved by 13.9%.(2)A parallel operation controller is designed among multiple IP cores.After optimization,the encryption rate of SM4 function end is increased by 69.4%,and that of AES function end is increased by 68.8%.(3)Design the interface conversion module and successfully mount the parallel encryption system on AXI bus.The correctness of the IP core and controller functions designed above is verified by VIVADO.Finally,after layout and wiring synthesis,it is burned into the XC7Z100CLC484-1 FPGA development board of ZYNQ-7000 series,and the test results show that the resource occupancy is 2717(LUT),3854(FF),34(BRAM)and166(I/O).