FPGA-based Ultra-Low Latency Quantitative Financial Computing Platform

As an efficient modern trading method,the proportion of high-frequency quantitative trading in the financial market is increasing year by year,and has gradually become one of the mainstream trading methods in the financial market.As an important part of high-frequency quantitative trading,the mastery of financial market is directly related to the income.Faster and more accurate market information means the opportunity to generate greater profits.The existing financial computing platforms mainly rely on CPU-based software solutions,which have extremely high processing latency and volatility.However,its specific application scenarios and network transmission requirements provide the possibility for hardware implementation.With its high parallelism,reconfiguration and low latency,FPGA can fully meet the real-time requirements of market data processing and network transmission in highfrequency quantitative trading.Therefore,the use of domain-specific hardware to build a quantitative financial computing platform has become the mainstream method to reduce the latency of financial data processing.This paper proposes an implementation of a FPGA-based ultra-low latency quantitative financial computing platform.The main contents are as follows.Firstly,for the communication scenarios in high-frequency quantitative trading,customize the FPGA hardware implementation of network communication function.Design and implement hardware customization based on FPGA for MAC layer protocol,IP protocol,ARP protocol,ICMP protocol,UDP protocol and TCP protocol.According to the specific network communication scenario,design a domain-specific TCP protocol offload engine to minimize the network communication latency on the basis of meeting the network communication function.The experimental results show that the minimum penetration latency of UDP protocol is 468.4ns,and the minimum penetration latency of TCP protocol offload engine is 494.8ns.Besides the maximum network bandwidth can reach 38.28Gbps.Secondly,for the market analysis scenario in high-frequency quantitative trading,customize the hardware implementation of data decoding and analysis functions.Aiming at tick data and order data in FAST financial compression protocol,design the decoder to realize the functions of field segmentation,data consolidation and data decoding.Meanwhile,use the decoded data to calculate the real-time market information,reconstruct the complete real-time market dictionary,and optimize the design and implementation of the storage of the market dictionary.The experimental results show that the financial market analysis module can process up to 80 securities at the same time,and the minimum decoding and reconstruction penetration delay of a single securities is 372.8ns.Thirdly,under the Vitis framework,integrate the functions of network communication,data decoding and analysis to build an ultra-low delay quantitative financial computing platform using OpenCL.Carry out parallel design in each functional module to optimize the data transmission path and build a full pipeline architecture.Optimize the memory architecture to improve the data transmission rate.The computing platform connects each module with AXI4Stream interface to improve the portability of the system.The experimental results show that the overall processing latency of FPGA solution is stable at 20μs,and almost no jitter exists.The maximum throughput of platform can reach 38.28Gbps.Compared with the software system solution based on Intel i9-9900x,the performance shows a 12x latency reduction and the throughput is 1.87 times higher than that of software solution.