Three-dimensional Framework Silicon Nanowire Growth Positioning Integration And Preparation Of Thin Film Transistor

The development of information technology represents the development of science and technology and a quantum leap forward for mankind.Among them,display technology,as an important carrier of information transmission,has been closely watched and studied by the industry for its powerful information exchange ability and wide comprehensive application.The flat panel display has an absolute dominant position in the display market through its advantages of thinness,high performance,low power consumption,long life and environmental protection.The next generation development trend will be large size,high definition,intelligent and flexible.Conventional amorphous silicon materials are difficult to meet the low-cost and high-current driving requirements of next-generation display technologies due to their low mobility,complex poly silicon material preparation process,and high laser crystallization costs,which limits their further development.Materials will be an important breakthrough.In recent years,the application of low-dimensional semiconductor materials on thin film transistors has shown good electrical properties,but the self-positioning problem has always limited its scale development.At the same time,Moore's Law has been continuing,not only in the field of microelectronics but also for large-area electronics.High integration and 3D architecture have become research hot spots in the display field.Silicon nanowires are expected to be the next generation of new thin film materials due to their unique structure(maximum capacitive coupling with dielectric layers),superior optoelectronic properties,transport properties,and compatibility with modern silicon process technologies.In this paper,a new planar solid-liquid-solid(IPSLS)nanowire growth technology can realize the direct integration of large-scale silicon nanowires on the surface area,thus reducing the high cost of "top-down"etching technology and operational difficulty of the vapor-liquid-solid(VLS)method to transfer vertical nanowires to a flat surface in large-area electronic device applications.At the same time,the stepping erosion technology is used to increase the integration degree of silicon nanowires to 8NW/?m.Based on this assembly,the three-dimensional silicon nanowire thin film transistor exhibits an on/off ratio greater than 107,a hole mobility of 60cm2/Vs and a leakage current with good electrical performance of 10-13 A.The application of silicon nanowire thin film transistors in the next generation display field has far-reaching significance.In general,the innovations of the paper are as follows:1.The IPSLS nanowire growth mode is used to precisely control the growth of nanowires,and the planar guided growth of large-area,self-aligned silicon nanowires is realized,and the success rate is as high as 90%.2.Innovatively proposed through the step erosion technology to achieve high-density silicon nanowires,to obtain ultra-low nanowire spacing of 100 nanometers,and without the use of any high-resolution lithography technology,reducing the cost of preparation.3.For the first time,the controllable integration of silicon nanowires in three-dimension is realized.A thin film transistor based on high density silicon nanowires was prepared.It provides theoretical and technical guidance for the application of self-assembled silicon nanowires in future 3D thin film transistors.