Study On Common Heterobonding Technique And Application Based On Ultrathin Intercalation

Heterogeneous integration is the inevitable trend of integrated circuit technology development in the post-Moore era,which can achieve smaller process scale,higher device integration density and more functional integration to meet the higher demand of integrated circuit system in the future.As one of the key technologies of heterogeneous integration,heterogeneous bonding technology has become the preferred technology for heterogeneous integration due to the high quality and easy processing of integrated devices,and has been widely used in advanced packaging,efficient thermal management,new photonic platforms and optoelectronic integration.Thesis,the common heterobonding technology based on ultrathin intercalation is mainly studied.The preparation technology of ultrathin intercalation and the complete process of low temperature heterobonding technology are successfully developed.The heterogeneous bonding of various cross-material systems is successfully realized,and the quality of the heterogeneous bonding chip is systematically characterized and analyzed.Lattice mismatch and thermal mismatch between different material systems are the main reasons affecting the yield and bonding quality,which is the main problem to achieve high quality cross-dimensional heterogeneous bonding.Through the systematic research on the characteristics of materials such as III-V materials,(super)wide band gap semiconductor,metal oxides,non-metallic oxides,etc.The ultrathin SiO2 intercalation layer was prepared by thermal oxidation,Atomic ayer Deposition(ALD),Plasma Enhanced Chemical Vapor Deposition(PECVD)and other processes.The lattice mismatch and thermal mismatch of different materials can be effectively alleviated by intercalation interface to realize heterogeneous bonding.The thickness of the bonding intercalation layer is 10 nm,which significantly reduces the thermal resistance of the bonding intercalation layer and improves the overall heat dissipation performance.There is no unified technical standard and performance index for the quality evaluation of bonded wafers.According to the requirements of the project,a set of bonding chip characterization technology was formed by comprehensively utilizing common characterization methods,including bonding strength characterization,cold and hot shock resistance test,thermal conductivity evaluation,interface stress characterization,interface morphology and interface composition analysis.Because the bonding interface is located inside,the thickness of bonding medium layer is too small,and the thermal conductivity of some substrates is too high,the measurement of thermal conductivity,stress and other parameters is difficult.Low temperature bonding technology can effectively avoid the interdiffusion of impurity atoms caused by traditional high temperature bonding(600-1000℃),thermal expansion and thermal stress between various materials and structures,and can meet the low temperature bonding requirements of epitaxial wafers and chips including device structures.The high activity bonding surface was obtained through surface treatment and the iterative optimization of heat treatment process,and the low temperature and high strength bonding across the material system was successfully realized.The process temperature range was 170250℃,and the bonding strength was over 1.0 J/m2.At present,a full set of plasma activated bonding,wet hydrophobic bonding and wet hydrophilic bonding processes has been developed,successfully achieving Si/Si,Si/InP,Si/SiC,SiC/InP,SiC/SiC,LiTaO3/SiC,LD Epitaxial/SiC,Nd:YVO4/SiC,Ce:YIG/SOI、YIG/SiN heterobonding,and the preliminary exploration in the fields of Distributed Feedback Laser(DFB)chip bonding,chip patch low temperature bonding without solution treatment,etc.