Research On Software-hardware Co-design Method Of Homomorphic Encryption Accelerator Based On FPGA

In the era of artificial intelligence and big data,data privacy has become a crucial issue.When users transfer private data to a third-party server to perform computing tasks,they tend to pay more attention to the privacy of the entire computing process.Fully homomorphic encryption(FHE)is a promising data privacy protection technology,which can perform complete computation on ciphertext to ensure user privacy.However,the polynomial data representation and complex algorithms in homomorphic encryption lead to a dramatic increase of computation,which limits the large-scale application of homomorphic encryption technology in the real world,especially in some scenarios requiring high real-time performance,such as deep learning.In addition,homomorphic encryption applications often have multiple design objectives,such as security level,approximate error and latency,thus the enormous design space also brings challenges to programmers.Designing a high performance and flexible homomorphic encryption accelerators has always been the common goal of academia and industry.At present,a full stack homomorphic encryption accelerator design framework is needed to provide convenience for programmers.In this thesis,we propose a hardware/software co-design framework for FPGA accelerator to implement fully homomorphic encryption technology based on CKKS(Cheon-Kim-Kimsong)scheme.We also point out that the KeySwitch operation is the main performance bottleneck of FHE computation,based on which we propose a low-latency KeySwitch module design that alleviates the data dependency within the KeySwitch operation.The proposed highlevel synthesis(HLS)design reduces the operation latency by up to 48%compared with the state-of-the-art FPGA-based implementation of KeySwitch module in Verilog.The high-level synthesis design allows programmers to change the full homomorphic encryption and hardware parameters more easily and flexibly for design space exploration.We propose an automated design space exploration framework that generates optimal encryption parameters and hardware configurations for a given application kernel and target FPGA(Field Programmable Gate Array)device.Experimental results on a set of real FHE application kernels and different FPGA devices show that the flexible design framework based on high-level synthesis design has better performance results in terms of security,approximation error and overall performance than the designs of fixed FHE parameter and hardware configurations.