Research On Power Reduction Of Demodulation Driver Circuit In Indirect Time-of-flight CMOS Image Sensor

Indirect Time-of-Flight(I-To F)CMOS image sensor(CIS)acquires depth information by indirectly measuring the propagation time of light between the object and the sensor to acquire depth information.It has advantages such as simple measurement principle,high integration,and low form factor.However,with increase of size of pixel array and modulation frequency,the power consumption of on-chip demodulation driver also increases exponentially,which brings problems in the application and design of I-To F CIS.Firstly,the increase of power consumption of demodulation drive circuit will directly lead to the increase of power consumption of I-To F CIS chip and reduce the battery life of mobile devices.Secondly,it will lead to the increase of chip temperature,which increases dark current and thermal noise and affects the imaging quality.Besides,to improve the power supply capacity and reduce the voltage drop,it is necessary to increase the width of power supply wiring,which will cause difficulties in routing and increase the chip area and cost.Aiming at the problem of high power consumption of demodulation driver,this dissertation proposes a low power demodulation method combining image resolution adjustment and image reconstruction.The method can effectively reduce the power consumption of demodulation driver while keep the depth accuracy.In this dissertation,the measurement principle of I-To F CIS is analyzed firstly,and an imaging model of is established for simulated imaging,then factors affecting the imaging depth accuracy are analyzed and simulations are carried out.Aiming at the problem of high power consumption caused by demodulation driver,circuit structured is first analyzed,and a model is established for power consumption calculation,then a power reduction method is proposed,which decreases the number of driven pixels at high modulation frequency by using a programmable resolution adjustment circuit to obtain an accurate low resolution depth map,and a low depth accuracy high resolution depth map is obtained at low modulation frequency,then a modified super-resolution algorithm is used to obtain an accurate high resolution solution depth map.Finally,the effectiveness of the proposed method is verified by simulation combined with imaging model and power consumption model,and the effectiveness of the method and the feasibility of hardware implementation are verified by FPGA.In the simulation,25 MHz and 100 MHz are used as the low modulation frequency and high modulation frequency,respectively.With the best scenario in depth accuracy kept,average power consumption decreases 38.47% and peak power consumption decreases 49.83% while depth error which represented by RMSE increases 8.08% merely.In the verification based on FPGA,the algorithm of image reconstruction in the proposed method is implemented.The result shows that comparing with processing by software,the processing effect is not significantly reduced,and the processing time is reduced from 1.839 s to 280 ms,and the power consumption of the algorithm is 0.233 W.The result proves the effectiveness of the proposed method and shows that hardware implementation of the proposed method is feasible.